在 VHDL (2008) 中声明类型之前使用类型

Question

是否可以在任何版本的 VHDL 中（可能是 2008 年）在声明类型之前使用它？

例如我在实体的架构中有这个数组声明：

type my_array is array (integer range <>) of my_type;

仍然在相同的体系结构部分，但在文件的后面我有这个：

type my_type is record 
    my_field: signed(31 downto 0);
end record;

现在这会在 Vivado 中出现以下错误：

[Synth 8-1031] my_type is not declared

解决办法当然是将记录声明移到数组声明之上。然而，随着类型数量的增加，这变得非常复杂和混乱（因为您基本上必须在考虑类型的依赖性的情况下对类型进行拓扑排序）。

每种主要编程语言都支持类似的东西，所以我想它可能也存在于 VHDL 中。我还依稀记得读过有关此内容已添加到 VHDL 2008 的信息，但找不到任何相关资源，而且我对 VHDL 2008 的快速测试是否定的。

那么是否可以在声明类型之前在 VHDL 中使用类型，假设类型声明仍在相同的体系结构、相同的文件中，但在下面几行？

Answer 1

是否可以在任何版本的 VHDL 中（可能是在 2008 年）在声明之前使用类型？

没有

IEEE 标准 1076-2008 6. 声明

6.1 General

The language defines several kinds of named entities that are declared explicitly or implicitly by declarations. Each entity’s name is defined by the declaration, either as an identifier or as an operator symbol or a character literal.
...
For each form of declaration, the language rules define a certain region of text called the scope of the declaration (see 12.2). ...

12.2 声明范围

The scope of a declaration, except for an architecture body, extends from the beginning of the declaration to the end of the immediately closing declarative region; the scope of an architecture body extends from the beginning to the end of the architecture body. In either case, this part of the scope of a declaration is called the immediate scope.

12.3 可见度

A declaration is visible only within a certain part of its scope; this part starts at the end of the declaration except in the declaration of a design unit other than a PSL verification unit, a package declaration, or a protected type declaration, in which case it starts immediately after the reserved word is occurring after the identifier of the design unit, a package declaration, or protected type declaration. This rule applies to both explicit and implicit declarations.

可见性规则阻止您在类型声明之前引用它。

此外，VHDL 不支持接口类型声明（泛型类型）以外的类型的前向声明，但支持子类型，如您的示例 my_array 所示。

Brian 指出泛型类型的用途有限，缺乏综合供应商支持以及 Peter Ashenden 的书 VHDL 2008 Just the New 中总结的类型操作限制（请参阅 6.5.3 接口类型声明）资料:

1.1 通用类型

VHDL-2008 defines a number of rules covering formal generic types and the ways they can be used. The formal generic type name can potentially represent any constrained type, except a file type or a protected type. The entity can only assume that operations available for all such types are applicable, namely: assignment; allocation using new; type qualification and type conversion; and equality and inequality operations. The formal generic type cannot be used as the type of a file element or an attribute. Moreover, it can only be used as the type of an explicitly declared constant or a signal (including a port) if the actual type is not an access type and does not contain a subelement of an access type. For signals, the predefined equality operator of the actual type is used for driver update and event detection.

Answer 2

请注意，对于访问类型，有一种特殊情况，其中不完整的类型声明可以是引用，以允许链表的类型，例如：

type value_cell;  -- Incomplete declaration

type value_ptr is access value_cell;  -- value_cell only for access type

type value_cell is record  -- Full declaration
  value     : bit_vector(0 to 3);
  next_cell : value_ptr;
end record value_cell;

然而，这不是使用声明前的类型，访问类型也不是可综合的，但它是测试平台代码的有用技术。

在 VHDL (2008) 中声明类型之前使用类型

Use a type before it's declared in VHDL (2008)

vhdl

xilinx

vivado