使用 vhdl-counter 的 If 语句
If statement using vhdl-counter
它的z DFF计数器从0计数到10,从10计数到0。有z开关在Ascending/Descending之间切换。这个网站上的一些人帮助我解决了 if 语句问题,但它看起来不允许在进程之外使用它,如果有人可以提供帮助并且有任何想法可以使用 when istead。将会是完美的。使用 planahead 设计这个计数器
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter_10 is
port(
clk, reset, pause: in std_logic;
q: out std_logic_vector(3 downto 0)
);
end counter_10;
architecture arc_counter of counter_10 is
constant M: integer:=10;
signal r_reg: unsigned(3 downto 0);
signal r_next: unsigned(3 downto 0);
begin
process(clk, reset, pause)
begin
if(reset='1') then r_reg <=(others=>'0');
elsif pause = '1' then
r_reg<=r_reg;
elsif (clk'event and clk='1') then
r_reg<=r_next;
end if;
end process;
------------------------------------------------------------------------
if (inc_dec='1') then
if (r_reg=(M-1)) then
r_next <= (others=>'0');
else
r_reg+1;
end if;
elsif (inc_dec='0') then
if (r_reg=(M-10)) then
r_next <= to_unsigned(9, 4);
else
r_reg-1;
end if;
end if;
------------------------------------------------------------------------
--Output logic
q<= std_logic_vector(r_reg);
end arc_counter;
错误依旧:
[HDLCompiler 806] Syntax error near "if".
[HDLCompiler 806] Syntax error near "then".
[HDLCompiler 806] Syntax error near "else".
[HDLCompiler 806] Syntax error near "then".
[HDLCompiler 806] Syntax error near "then".
[HDLCompiler 806] Syntax error near "else".
请注意您缺少模式为 inc_dec 的端口。
如评论中所述,您的 if 语句不是并发语句,需要进入流程。
您对 r_next 的递增和递减对于 VHDL 不正确。
暂停不应该是异步的它推断出 r_reg 寄存器之后的锁存器。
修复所有这些,它看起来像这样:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter_10 is
port (
clk: in std_logic;
reset: in std_logic;
pause: in std_logic;
inc_dec: in std_logic; -- ADDED
q: out std_logic_vector(3 downto 0)
);
end counter_10;
architecture arc_counter of counter_10 is
-- constant M: integer := 10; -- not needed
signal r_reg: unsigned(3 downto 0);
signal r_next: unsigned(3 downto 0);
begin
UNLABELED:
process(clk, reset)
begin
if reset = '1' then
r_reg <= (others=>'0');
-- elsif pause = '1' then
-- r_reg <= r_reg;
elsif clk'event and clk = '1' and not pause = '1' then
r_reg <= r_next;
end if;
end process;
ADDED_PROCESS:
process (inc_dec, r_reg)
begin
if inc_dec = '1' then
if r_reg = 9 then -- r_reg = M - 1 then
r_next <= (others => '0');
else
r_next <= r_reg + 1; -- r_reg+1;
end if;
elsif inc_dec = '0' then
if r_reg = 0 then -- r_reg = M - 10 then
r_next <= to_unsigned(9, 4);
else
r_next <= r_reg - 1; -- r_reg-1;
end if;
end if;
end process;
--Output
q<= std_logic_vector(r_reg);
end arc_counter;
大约现在有人肯定会插话并写道这两个过程可以合并。
这可能看起来像:
architecture foo of counter_10 is
-- constant M: integer := 10; -- not needed
signal r_reg: unsigned(3 downto 0);
signal r_next: unsigned(3 downto 0);
begin
SINGLE_PROCESS:
process(clk, reset)
begin
if reset = '1' then
r_reg <= (others=>'0');
-- elsif pause = '1' then
-- r_reg <= r_reg;
elsif clk'event and clk = '1' and not pause = '1' then
if inc_dec = '1' then
if r_reg = 9 then
r_reg <= (others => '0');
else
r_reg <= r_reg + 1;
end if;
elsif inc_dec = '0' then -- and this could be simply else
if r_reg = 0 then
r_reg <= to_unsigned(9, 4);
else
r_reg <= r_reg - 1;
end if;
end if;
r_reg <= r_next;
end if;
end process;
--Output
q<= std_logic_vector(r_reg);
end architecture;
有待进一步改进或替代实施。
它的z DFF计数器从0计数到10,从10计数到0。有z开关在Ascending/Descending之间切换。这个网站上的一些人帮助我解决了 if 语句问题,但它看起来不允许在进程之外使用它,如果有人可以提供帮助并且有任何想法可以使用 when istead。将会是完美的。使用 planahead 设计这个计数器
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter_10 is
port(
clk, reset, pause: in std_logic;
q: out std_logic_vector(3 downto 0)
);
end counter_10;
architecture arc_counter of counter_10 is
constant M: integer:=10;
signal r_reg: unsigned(3 downto 0);
signal r_next: unsigned(3 downto 0);
begin
process(clk, reset, pause)
begin
if(reset='1') then r_reg <=(others=>'0');
elsif pause = '1' then
r_reg<=r_reg;
elsif (clk'event and clk='1') then
r_reg<=r_next;
end if;
end process;
------------------------------------------------------------------------
if (inc_dec='1') then
if (r_reg=(M-1)) then
r_next <= (others=>'0');
else
r_reg+1;
end if;
elsif (inc_dec='0') then
if (r_reg=(M-10)) then
r_next <= to_unsigned(9, 4);
else
r_reg-1;
end if;
end if;
------------------------------------------------------------------------
--Output logic
q<= std_logic_vector(r_reg);
end arc_counter;
错误依旧:
[HDLCompiler 806] Syntax error near "if".
[HDLCompiler 806] Syntax error near "then".
[HDLCompiler 806] Syntax error near "else".
[HDLCompiler 806] Syntax error near "then".
[HDLCompiler 806] Syntax error near "then".
[HDLCompiler 806] Syntax error near "else".
请注意您缺少模式为 inc_dec 的端口。
如评论中所述,您的 if 语句不是并发语句,需要进入流程。
您对 r_next 的递增和递减对于 VHDL 不正确。
暂停不应该是异步的它推断出 r_reg 寄存器之后的锁存器。
修复所有这些,它看起来像这样:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter_10 is
port (
clk: in std_logic;
reset: in std_logic;
pause: in std_logic;
inc_dec: in std_logic; -- ADDED
q: out std_logic_vector(3 downto 0)
);
end counter_10;
architecture arc_counter of counter_10 is
-- constant M: integer := 10; -- not needed
signal r_reg: unsigned(3 downto 0);
signal r_next: unsigned(3 downto 0);
begin
UNLABELED:
process(clk, reset)
begin
if reset = '1' then
r_reg <= (others=>'0');
-- elsif pause = '1' then
-- r_reg <= r_reg;
elsif clk'event and clk = '1' and not pause = '1' then
r_reg <= r_next;
end if;
end process;
ADDED_PROCESS:
process (inc_dec, r_reg)
begin
if inc_dec = '1' then
if r_reg = 9 then -- r_reg = M - 1 then
r_next <= (others => '0');
else
r_next <= r_reg + 1; -- r_reg+1;
end if;
elsif inc_dec = '0' then
if r_reg = 0 then -- r_reg = M - 10 then
r_next <= to_unsigned(9, 4);
else
r_next <= r_reg - 1; -- r_reg-1;
end if;
end if;
end process;
--Output
q<= std_logic_vector(r_reg);
end arc_counter;
大约现在有人肯定会插话并写道这两个过程可以合并。
这可能看起来像:
architecture foo of counter_10 is
-- constant M: integer := 10; -- not needed
signal r_reg: unsigned(3 downto 0);
signal r_next: unsigned(3 downto 0);
begin
SINGLE_PROCESS:
process(clk, reset)
begin
if reset = '1' then
r_reg <= (others=>'0');
-- elsif pause = '1' then
-- r_reg <= r_reg;
elsif clk'event and clk = '1' and not pause = '1' then
if inc_dec = '1' then
if r_reg = 9 then
r_reg <= (others => '0');
else
r_reg <= r_reg + 1;
end if;
elsif inc_dec = '0' then -- and this could be simply else
if r_reg = 0 then
r_reg <= to_unsigned(9, 4);
else
r_reg <= r_reg - 1;
end if;
end if;
r_reg <= r_next;
end if;
end process;
--Output
q<= std_logic_vector(r_reg);
end architecture;
有待进一步改进或替代实施。