VHDL 时钟 LED 序列

Question

这是我第一次 post 访问此站点，我正在为我的电子学位学习 VHDL，并且必须编写一个程序来在每个时钟脉冲处为一个序列更改 LED 序列。我想我已经破解了它，但这是我第一次使用 VHDL 语言，所以我不确定 iv 是否使用了最有效的方法。我的代码是。

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;


entity REG_LED is
 PORT(CLK:      IN  std_logic;              -- CLK input
     LEDS:      Out std_logic_vector (4 downto 0):= "11111"); -- initialise      output
End REG_LED;

ARCHITECTURE behavioral OF REG_LED IS
 SIGNAL Temp:   std_logic_vector (3 downto 0):= "0000"; -- initailise comparison signal
  BEGIN
    CLK_0_Process:  PROCESS (CLK)   -- begin 
    BEGIN 
    if Temp <= "0000" Then          -- State 0          
        if rising_edge(CLK) Then
            Temp <= "0001" ;
            LEDS <= "00001";    
        END IF;
     ELSIF Temp <= "0001" Then  -- State 1
        if rising_edge(CLK) Then
            Temp <= "0010" ;
            LEDS <= "00001";
     END IF;
     ELSIF Temp <= "0010" Then  -- State 2
        if rising_edge(CLK) Then
            Temp <= "0011" ;
            LEDS <= "11111";
     END IF;
     ELSIF Temp <= "0011" Then  -- State 3  
        if rising_edge(CLK) Then
            Temp <= "0100" ;
            LEDS <= "00000";
     END IF;
     ELSIF Temp <= "0100" Then  -- State 4
        if rising_edge(CLK) Then
            Temp <= "0101" ;
            LEDS <= "11111";
     END IF;
     ELSIF Temp <= "0101" Then  -- State 5
        if rising_edge(CLK) Then
            Temp <= "0110" ;
            LEDS <= "00100";
     END IF;
     ELSIF Temp <= "0110" Then  -- State 6
        if rising_edge(CLK) Then
            Temp <= "0111" ;
            LEDS <= "01010";
     END IF;
     ELSIF Temp <= "0111" Then  -- State 7
        if rising_edge(CLK) Then
            Temp <= "1000" ;
            LEDS <= "10001";
     END IF;
     ELSIF Temp <= "1000" Then  -- State 8
        if rising_edge(CLK) Then
                LEDS <= "10001";
     END IF;
    END IF;
    END PROCESS ;
END behavioral;

谁能告诉我是否有我错过的替代路线？

非常感谢

Answer 1

好吧，我会说这是一种低效的方法，但是，就像任何语言一样，你学得越多，你编写的代码就越高效。更重要的是，您的代码不可综合：您无法直接从中生产硬件。

如果您希望您的代码可综合，您应该坚持使用模板。这是一个没有异步复位的时序逻辑模板，所有综合工具都应该理解它：

process(CLK)  -- nothing else should go in the sensitivity list
begin
    -- never put anything here
    if rising_edge(CLK) then  -- or falling_edge(CLK)
        -- put the synchronous stuff here
        -- ie the stuff that happens on the rising or falling edge of the clock
    end if;
     -- never put anything here
end process;

因此，您需要重构代码以适应此模板，即：

process(CLK)
begin
  if rising_edge(CLK) then
    if Temp <= "0000" Then          -- State 0          
      Temp <= "0001" ;
      LEDS <= "00001";    
    ELSIF Temp <= "0001" Then  -- State 1
      Temp <= "0010" ;
      LEDS <= "00001";
    ELSIF Temp <= "0010" Then  -- State 2

    -- etc etc

    end if;
  end if;
end process;

看到 Temp 只是在计数，在代码中使用行 Temp <= Temp + 1; 会更有效（就解决方案的优雅性和代码行数而言）使用 case 语句（在单独的进程中）驱动 LEDS 信号。但是你必须了解 类型转换 和 numeric_std 包和 case 语句，大概你还没有学过。

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