VHDL 时钟序列 Q3

Question

我必须创建一个 VHDL 序列，它只需要一个时钟输入并输出 5 个 LED 序列 see picture 我认为使用 std_logic_vector 然后我可以将每个矢量输出连接到单个 LED 以创建此序列是正确的，还是我错过了 std_logic_vector 的解释？

我使用的代码是

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all; -- i have used this package as my CLK-CNT signal    counts in integer format rather than binary and i am performing an ADD sum of   the CLK_CNT


entity REG_LED is
 PORT(CLK:      IN  std_logic;              -- CLK input
     LEDS:      Out std_logic_vector (4 downto 0) ); -- initialise output
End REG_LED;

ARCHITECTURE behavioral OF REG_LED IS
SIGNAL CLK_CNT:     integer range 0 to 9:= 0; -- initailise comparison signal used for counting clock pulses.
 -- This signal will be used by the program to recognise where in the sequnce the program is and thus determine the next state required for the sequence.
BEGIN

    CLK_Process:    PROCESS (CLK)   -- begin the CLK_CNT Process
    BEGIN 

    if rising_edge(CLK) Then
        if CLK_CNT = 8 then 
            CLK_CNT <= 0; -- this resets the clock pulse count to 0
        else
            CLK_CNT <= CLK_CNT + 1 ; -- used to count each clock pulse upto the reset 
        End if;
-- this process has been kept seperate to the LED output process in order to isolate the event from the output process and limit the possiblities of errors         
    END IF;

    END PROCESS ;

    LED_PROCESS: Process (CLK_CNT) -- LED Outputs based on Temp count

    BEGIN -- begin the output sequence 

        Case CLK_CNT is 
-- i use a case statement to compare the value of the CLK_CNT signal and produce the required LEDS output 
-- this ensures the 
            When 0 =>
                LEDS <= "11111"; -- S0 when clock count is 0
            When 1 =>
                LEDS <= "00001"; -- S1 when clock count is 1
            When 2 =>       
                LEDS <= "00001"; -- S2 when clock count is 2
            When 3 =>
                LEDS <= "11111"; -- S3 when clock count is 3
            When 4 =>
                LEDS <= "00000"; -- S4 when clock count is 4
            When 5 =>
                LEDS <= "11111"; -- S5 when clock count is 5
            When 6 =>
                LEDS <= "00100"; -- S6 when clock count is 6
            When 7 =>
                LEDS <= "01010"; -- S7 when clock count is 7
            When 8 =>
                LEDS <= "10001"; -- S8 when clock count is 8 this is the final clock count state

            When others => 
                LEDS <= "11111"; -- Restart Sequence

        End Case;               

    End Process;
END behavioral;

我已经模拟了波形并且它产生了序列所需的 5 个输出但是这个输出可以用来驱动 5 个不同的 LED 还是它只是一个端口输出的 5 位字？我是 VHDL 的新手，所以任何帮助将不胜感激

Answer 1

您的代码看起来不错，如果您的模拟表明它可以根据您的需要运行，那么您几乎可以开始了。

一个std_logic_vector其实就是多根电线（总线）。您必须考虑它的物理含义，因为这是您对 FPGA 编程时真正发生的事情。所以是的，您可以将总线拆分（或拆分）为单独的线路。可以这样做：

signal LED_LINE_0 : std_logic;
signal LED_LINE_1 : std_logic;
LED_LINE_0 <= LEDS(0);
LED_LINE_1 <= LEDS(1);

...等等。这一次撕掉一根电线。您还可以通过一次撕掉多条电线将总线拆分成更小的总线。例如

signal small_bus_1 : std_logic_vector(1 downto 0);
signal small_bus_2 : std_logic_vector(1 downto 0);
signal big_bus : std_logic_vector(3 downto 0);

small_bus_1 <= big_bus(3 downto 2);
small_bus_2 <= big_bus(1 downto 0);

然后您可以在您的约束文件中写入（或使用您的 FPGA 品牌 IDE 中的 GUI）来指定您希望这些 std_logic 中的每一个在 FPGA 上的哪个引脚分配给（驱动您需要的 LED）。

VHDL 时钟序列 Q3

VHDL CLOCK SEQUENCE Q3

vhdl

clock

led