8位加法器不能正常工作

Question

我正在编写 Verilog 代码以使用 8 个全加器构造一个 8 位加法器。该 8 位加法器应为每个 8 位总线添加 2 个输入输入。这是单个全加器的代码：

module FullAdder(
input a_,
input b_,
input cin_,
output sout_,
output cout_
);
wire temp1, temp2, temp3;

assign sout_ = a_ ^ b_ ^ cin_;
assign cout_ = ((a_ & b_) | (b_ & cin_) | (cin_ & a_));

endmodule

这里是 8 位加法器模块的代码，它将调用全加器 8 次。

module EightBitAdder(
input [7:0] a,
input [7:0] b,
//input cin,
output cout,  //carry; will be sent as OP, but won't be further used.
output [7:0] sout  //sum, sent as OP
);

wire try;

begin 
FullAdder mg0(.a_(a[0]), .b_(b[0]), .cin_(0), .cout_(try), .sout_(sout[0]));
FullAdder mg1(.a_(a[1]), .b_(b[1]), .cin_(try), .cout_(try), .sout_(sout[1]));
FullAdder mg2(.a_(a[2]), .b_(b[2]), .cin_(try), .cout_(try), .sout_(sout[2]));
FullAdder mg3(.a_(a[3]), .b_(b[3]), .cin_(try), .cout_(try), .sout_(sout[3]));
FullAdder mg4(.a_(a[4]), .b_(b[4]), .cin_(try), .cout_(try), .sout_(sout[4]));
FullAdder mg5(.a_(a[5]), .b_(b[5]), .cin_(try), .cout_(try), .sout_(sout[5]));
FullAdder mg6(.a_(a[6]), .b_(b[6]), .cin_(try), .cout_(try), .sout_(sout[6]));
FullAdder mg7(.a_(a[7]), .b_(b[7]), .cin_(try), .cout_(try), .sout_(sout[7]));
end
endmodule

问题是输出显示不正确。它总是显示第一位，然后用无关 (X) 填充其余位。这可能是什么问题？

Answer 1

相同的 try 线由所有 8 个全加器驱动，因此如果两者都用 0 和 [=15 驱动，这很可能导致 X 值=] 从全加器执行。

考虑改用进位线，例如：

wire [7:0] cout;

并对不同的全加器使用不同的位，例如：

FullAdder mg0(.a_(a[0]), .b_(b[0]), .cin_(0), .cout_(cout[0]), .sout_(sout[0]));
FullAdder mg1(.a_(a[1]), .b_(b[1]), .cin_(cout[0]), .cout_(cout[1]), .sout_(sout[1]));
...

8位加法器不能正常工作

8bit adder not working properly

verilog

hdl