ALU设计错误

Question

我想在 VHDL 中设计一个 8 位 alu，但我得到了这个错误，我认为这与我的输入声明为 bit_vectors 有关。是真的吗？

** Error: C:/Programs/Modeltech_pe_edu_10.4a/examples/alu.vhdl(19): No feasible entries for infix operator "+".
** Error: C:/Programs/Modeltech_pe_edu_10.4a/examples/alu.vhdl(19): Type error resolving infix expression "+" as type std.STANDARD.BIT_VECTOR.
** Error: C:/Programs/Modeltech_pe_edu_10.4a/examples/alu.vhdl(21): No feasible entries for infix operator "-".
** Error: C:/Programs/Modeltech_pe_edu_10.4a/examples/alu.vhdl(21): Type error resolving infix expression "-" as type std.STANDARD.BIT_VECTOR.
** Error: C:/Programs/Modeltech_pe_edu_10.4a/examples/alu.vhdl(23): No feasible entries for infix operator "-".
** Error: C:/Programs/Modeltech_pe_edu_10.4a/examples/alu.vhdl(23): Type error resolving infix expression "-" as type std.STANDARD.BIT_VECTOR.
** Error: C:/Programs/Modeltech_pe_edu_10.4a/examples/alu.vhdl(25): No feasible entries for infix operator "+".
** Error: C:/Programs/Modeltech_pe_edu_10.4a/examples/alu.vhdl(25): Type error resolving infix expression "+" as type std.STANDARD.BIT_VECTOR.
** Error: C:/Programs/Modeltech_pe_edu_10.4a/examples/alu.vhdl(40): VHDL Compiler exiting

这是我的模块：

entity alu is
 port ( bus_a : in bit_vector(7 downto 0);
 bus_b : in bit_vector(7 downto 0);
 state : in bit_vector (2 downto 0);
 out_c : out bit_vector(7 downto 0));
end alu;


architecture behave of alu is

begin

process(bus_a, bus_b, state)

begin
case state is
 when "000" => 
 out_c<= bus_a + bus_b; --addition 
 when "001" => 
 out_c<= bus_a - bus_b; --subtraction 
 when "010" => 
 out_c<= bus_a - 1; --sub 1 
 when "011" => 
 out_c<= bus_a + 1; --add 1 
 when "100" => 
 out_c<= bus_a and bus_b; --AND gate 
 when "101" => 
 out_c<= bus_a or bus_b; --OR gate 
 when "110" => 
 out_c<= not bus_a ; --NOT gate 
 when "111" => 
 out_c<= bus_a xor bus_b; --XOR gate 
 when others =>
 NULL;
end case; 

end process; 

end architecture behave;

您知道原因吗？也许您对这个问题还有其他建议？提前致谢！

Answer 1

一个bit_vector只是bit的集合，没有任何内在价值，所以你必须告诉VHDL如何在bit_vector理解为一个值之前使用加法 (+).

这样的算术运算符是有意义的

看一下 numeric_bit 包，它的类型 signed 和 unsigned 作为 bit 的数组，您可以指定 [=11] =] 在进行加法时被视为有符号或无符号值。

因此，对于无符号加法，库的使用和转换如下所示：

library ieee;
use ieee.numeric_bit.all;
...
out_c <= bit_vector(unsigned(bus_a) + unsigned(bus_b));  --addition

但通常使用 std_logic_vector 而不是 bit_vector，因此您可以考虑查看 std_logic_1164 和 numeric_std 包。

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