如何在 VHDL 架构中使用实体
How to use an entity inside an architecture in VHDL
我的目的是实现一个使用按钮实体的键盘实体。
所以我写了下面的VHDL代码:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Keyboard is
port ( ck, stop : in STD_LOGIC;
data_in : in STD_LOGIC_VECTOR (11 downto 0);
data_out : out STD_LOGIC_VECTOR (3 downto 0));
end Keyboard;
entity Button is
port ( clk : in STD_LOGIC ;
signal_in : in STD_LOGIC;
output : out STD_LOGIC);
end Button;
architecture test of Keyboard is
signal NUM : STD_LOGIC_VECTOR (11 downto 0) := (others=>'0');
component Button is
port ( clk : in STD_LOGIC ;
signal_in : in STD_LOGIC;
output : out STD_LOGIC);
end component;
begin
num_0 : entity Button port map(ck,data_in(0),NUM(0));
num_1 : entity Button port map(ck=>clk,data_in(1)=>signal_in,NUM(1)=>output);
num_2 : entity Button port map(ck=>clk,data_in(2)=>signal_in,NUM(2)=>output);
num_3 : entity Button port map(ck=>clk,data_in(3)=>signal_in,NUM(3)=>output);
num_4 : entity Button port map(ck=>clk,data_in(4)=>signal_in,NUM(4)=>output);
num_5 : entity Button port map(ck=>clk,data_in(5)=>signal_in,NUM(5)=>output);
num_6 : entity Button port map(ck=>clk,data_in(6)=>signal_in,NUM(6)=>output);
num_7 : entity Button port map(ck=>clk,data_in(7)=>signal_in,NUM(7)=>output);
num_8 : entity Button port map(ck=>clk,data_in(8)=>signal_in,NUM(8)=>output);
num_9 : entity Button port map(ck=>clk,data_in(9)=>signal_in,NUM(9)=>output);
num_on : entity Button port map(ck=>clk,data_in(10)=>signal_in,NUM(10)=>output);
num_off : entity Button port map(ck=>clk,data_in(11)=>signal_in,NUM(11)=>output);
output <= "0000" when NUM = "000000000001" else --0
"0001" when NUM = "000000000010" else --1
"0010" when NUM = "000000000100" else --2
"0011" when NUM = "000000001000" else --3
"0100" when NUM = "000000010000" else --4
"0101" when NUM = "000000100000" else --5
"0110" when NUM = "000001000000" else --6
"0111" when NUM = "000010000000" else --7
"1000" when NUM = "000100000000" else --8
"1001" when NUM = "001000000000" else --9
"1010" when NUM = "010000000000" else --ON
"1100" when NUM = "100000000000" else --OFF
"1111";
end test;
architecture EdgeDetector of Button is
signal signal_d:STD_LOGIC;
begin
process(clk)
begin
if clk= '1' and clk'event then
signal_d<=signal_in;
end if;
end process;
output<= (not signal_d) and signal_in;
end EdgeDetector;
通过在 QuartusII 上开始编译,我遇到了以下错误:
Error (10482): VHDL error at PitAlarm.vhd(11): object "STD_LOGIC" is
used but not declared
但是我不明白 "not declared" 是什么意思 ???
使用 "direct entity instantiation" 可以明确地将实体从特定库中绑定出来,而不是使用 "configurations" 或某些默认策略来查找匹配的实体。因此,num_0 : entity Work.Button port map(...);
- 请注意显式库名称(此处为 Work
)。
您发现的具体错误
std_logic not declared
来自图书馆条款的可见性规则。
Button 自己的 entity/arch 通常会在一个单独的文件中,在编译顶层之前单独编译。
然后它将有自己的 library/use 声明 std_logic
的库的子句。
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
同一文件中有多个实体,此条款仅适用于以下实体声明(并使其在相应架构中可见)。
因此您需要在文件中的每个实体声明之前重复这两行。
我的目的是实现一个使用按钮实体的键盘实体。
所以我写了下面的VHDL代码:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Keyboard is
port ( ck, stop : in STD_LOGIC;
data_in : in STD_LOGIC_VECTOR (11 downto 0);
data_out : out STD_LOGIC_VECTOR (3 downto 0));
end Keyboard;
entity Button is
port ( clk : in STD_LOGIC ;
signal_in : in STD_LOGIC;
output : out STD_LOGIC);
end Button;
architecture test of Keyboard is
signal NUM : STD_LOGIC_VECTOR (11 downto 0) := (others=>'0');
component Button is
port ( clk : in STD_LOGIC ;
signal_in : in STD_LOGIC;
output : out STD_LOGIC);
end component;
begin
num_0 : entity Button port map(ck,data_in(0),NUM(0));
num_1 : entity Button port map(ck=>clk,data_in(1)=>signal_in,NUM(1)=>output);
num_2 : entity Button port map(ck=>clk,data_in(2)=>signal_in,NUM(2)=>output);
num_3 : entity Button port map(ck=>clk,data_in(3)=>signal_in,NUM(3)=>output);
num_4 : entity Button port map(ck=>clk,data_in(4)=>signal_in,NUM(4)=>output);
num_5 : entity Button port map(ck=>clk,data_in(5)=>signal_in,NUM(5)=>output);
num_6 : entity Button port map(ck=>clk,data_in(6)=>signal_in,NUM(6)=>output);
num_7 : entity Button port map(ck=>clk,data_in(7)=>signal_in,NUM(7)=>output);
num_8 : entity Button port map(ck=>clk,data_in(8)=>signal_in,NUM(8)=>output);
num_9 : entity Button port map(ck=>clk,data_in(9)=>signal_in,NUM(9)=>output);
num_on : entity Button port map(ck=>clk,data_in(10)=>signal_in,NUM(10)=>output);
num_off : entity Button port map(ck=>clk,data_in(11)=>signal_in,NUM(11)=>output);
output <= "0000" when NUM = "000000000001" else --0
"0001" when NUM = "000000000010" else --1
"0010" when NUM = "000000000100" else --2
"0011" when NUM = "000000001000" else --3
"0100" when NUM = "000000010000" else --4
"0101" when NUM = "000000100000" else --5
"0110" when NUM = "000001000000" else --6
"0111" when NUM = "000010000000" else --7
"1000" when NUM = "000100000000" else --8
"1001" when NUM = "001000000000" else --9
"1010" when NUM = "010000000000" else --ON
"1100" when NUM = "100000000000" else --OFF
"1111";
end test;
architecture EdgeDetector of Button is
signal signal_d:STD_LOGIC;
begin
process(clk)
begin
if clk= '1' and clk'event then
signal_d<=signal_in;
end if;
end process;
output<= (not signal_d) and signal_in;
end EdgeDetector;
通过在 QuartusII 上开始编译,我遇到了以下错误:
Error (10482): VHDL error at PitAlarm.vhd(11): object "STD_LOGIC" is used but not declared
但是我不明白 "not declared" 是什么意思 ???
使用 "direct entity instantiation" 可以明确地将实体从特定库中绑定出来,而不是使用 "configurations" 或某些默认策略来查找匹配的实体。因此,num_0 : entity Work.Button port map(...);
- 请注意显式库名称(此处为 Work
)。
您发现的具体错误
std_logic not declared
来自图书馆条款的可见性规则。
Button 自己的 entity/arch 通常会在一个单独的文件中,在编译顶层之前单独编译。
然后它将有自己的 library/use 声明 std_logic
的库的子句。
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
同一文件中有多个实体,此条款仅适用于以下实体声明(并使其在相应架构中可见)。
因此您需要在文件中的每个实体声明之前重复这两行。