我如何在 LLVM 的 foreach 循环中引用寄存器？

Question

我目前正在尝试通过 TableGen 定义我使用的体系结构寄存器。应该有 2 个计算块 XR 和 YR 以及一个引用它们的伪块 XYR。例如，XYR3 是包含 X3 和 Y3 的向量伪寄存器。

// Classes for registers of my namespace.

class TigerSHARCReg<bits<5> num, string n, list<string> altNames = []> :
  Register<n, altNames>
{
  field bits<5> Num = num;
  let Namespace = "TigerSHARC";
}

class TigerSHARCVReg<bits<5> num, string n, list<TigerSHARCReg> subregs, list<SubRegIndex> indices = []> :
  RegisterWithSubRegs<n, subregs>
{
  field bits<5> Num = num;
  let Namespace = "TigerSHARC";
    let SubRegIndices = indices;
}

class TigerSHARCSubRegIndex<int size, int offset> : SubRegIndex<size, offset>
{
    let Namespace = "TigerSHARC";
}

// === === ===

// XR registers and XR register class
foreach num = 0-31 in
def XR#num : TigerSHARCReg<num, "XR"#num>;

def XR : RegisterClass<"TigerSHARC", [i32, f32], 32, 
    (sequence "XR%u", 0, 31)>;


// YR registers and YR register class
foreach num = 0-31 in
def YR#n : TigerSHARCReg<num, "YR"#num>;

def YR : RegisterClass<"TigerSHARC", [i32, f32], 32, 
    (sequence "YR%u", 0, 31)>;

// There only two subregisters in each XYR
def XYRsub0 : TigerSHARCSubRegIndex<1, 0>;
def XYRsub1 : TigerSHARCSubRegIndex<1, 0>;


// XYR registers and XYR register class
foreach num = 0-31 in
def XYR#num : TigerSHARCVReg<0, "XYR0", [XR#num, YR#num], [XYRsub0, XYRsub1]>;

def XYR : RegisterClass<"TigerSHARC", [v2i32], 32, (sequence "XYR%u", 0, 31)>;

问题出在这些行中：

foreach num = 0-31 in
def XYR#num : TigerSHARCVReg<0, "XYR0", [XR#num, YR#num], [XYRsub0, XYRsub1]>;

"#" 仅连接字符串，因此 [XR#num, YR#num] 是不正确的表示法。我试过 XR[num] 但它似乎也不起作用。

有没有办法在循环中引用现有的寄存器？

还有，我做对了吗？

Answer 1

看起来应该使用 [!cast< MyTypeReg >("XR"#n), !cast< MyTypeReg >("YR"# 而不是 [XR#num, YR#num] n)]. !cast(a) 查找符号 table 字符串 a.

我如何在 LLVM 的 foreach 循环中引用寄存器？

How do I refer to a register in a foreach loop in LLVM?

foreach

llvm