FPGA 上的伺服

Question

我正在尝试在基于 Spartan-6 的 FPGA 上运行伺服。

我的代码如下：

`timescale 1ns / 1ps


/*
 1 pin for servo--ORANGE CABLE
 red cable-- 5V, brown cable-- GND. 
 Position "0" (1.5 ms pulse) is middle, 
 "90" (~2ms pulse) is all the way to the right,
 "-90" (~1 ms pulse) is all the way to the left.  
 servo stuff:
 http://www.micropik.com/PDF/SG90Servo.pdf
 */


 //All i need to do is set SERVOPWM to 1 and 0 with delays i think
module ServoTestNShit(input M_CLOCK,
                             output [7:0] IO_LED, // IO Board LEDs
                             output reg SERVOPWM);    

    assign IO_LED = 7'b1010101; // stagger led lights just cause

   reg [15:0] counter;

    //use counter to have a 1ms or 2ms or 1.5ms duty cycle for a while inorder to actually run
    //because run it this way is asking the servo to move for 1.5ms so it cant atually move that fast
    always @* 
    begin

        for(counter = 0; counter < 3000; counter = counter + 1)
        begin
        SERVOPWM = 1; 
        #2;
        SERVOPWM = 0;
        #2;
        SERVOPWM = 1; 
        #2;
        SERVOPWM = 0;
        #2;
        SERVOPWM = 1; 
        #2;
        SERVOPWM = 0;
        #2;
        end

        for(counter = 0; counter < 3000; counter = counter + 1)
        begin
        SERVOPWM = 1; 
        #1;
        SERVOPWM = 0;
        #2;
        SERVOPWM = 1; 
        #1;
        SERVOPWM = 0;
        #2;
        SERVOPWM = 1; 
        #1;
        SERVOPWM = 0;
        #2;
        end

    end


endmodule

我的 ucf 文件几乎只是：

# Clock signal 

NET "M_CLOCK" LOC = P123;


NET "SERVOPWM" LOC = P121 ;//0P1

所以在我的脑海中，我的代码将创建一个脉冲波，首先一直向右，通过设置高 2 毫秒，然后低，然后高 2 毫秒，等等并重复。然后，一路向左，持续 1 毫秒，等等。我认为这个问题会相对简单，因为我所做的只是向 IO 引脚发送 1 或 0，并且我将伺服连接到 5v、接地和有问题的 IO 引脚。

有什么东西stupid/obvious/easy是我遗漏的吗？还是我遗漏了某些概念？

提前感谢您的帮助！科迪

Answer 1

延迟 (#) 语句未在 verilog 中合成。这样它只会输出最终值。您应该将输出与时钟同步。

我的做法是

always @ (posedge clk)
begin
   counter <= counter+1;
end

always @ (negedge clk)
begin
   SERVOPWM <= (counter <= pwm_value);
end

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