如何解决这些警告？ | VHDL编程

Question

因此，我尝试在 FPGA 上实现 I2C 主控，但出现以下错误。有人知道如何解决吗？谢谢！

WARNING:Xst:646 - Signal <thirdaddress> is assigned but never used. This unconnected signal will be trimmed during the optimization process.

WARNING:Xst:646 - Signal <secondaddress> is assigned but never used. This unconnected signal will be trimmed during the optimization process.

WARNING:Xst:646 - Signal <firstaddress> is assigned but never used. This unconnected signal will be trimmed during the optimization process.

WARNING:Xst:736 - Found 1-bit latch for signal <Mtridata_sda> created at line 44. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.

WARNING:Xst:736 - Found 1-bit latch for signal <Mtrien_sda> created at line 44. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.

WARNING:Xst:737 - Found 3-bit latch for signal <sendcount>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.

WARNING:Xst:1293 - FF/Latch <XLXI_9/sendcount_2> has a constant value of 0 in block <top_level>. This FF/Latch will be trimmed during the optimization process.

WARNING:Xst:1293 - FF/Latch <XLXI_9/sendcount_1> has a constant value of 0 in block <top_level>. This FF/Latch will be trimmed during the optimization process.

WARNING:Xst:1293 - FF/Latch <XLXI_9/sendcount_0> has a constant value of 0 in block <top_level>. This FF/Latch will be trimmed during the optimization process.

WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <XLXI_9/current_state_FSM_FFd1> has a constant value of 0 in block <top_level>. This FF/Latch will be trimmed during the optimization process.

WARNING:Xst:1294 - Latch <XLXI_9/Mtridata_sda> is equivalent to a wire in block <top_level>.

WARNING:Xst:1294 - Latch <XLXI_9/Mtrien_sda> is equivalent to a wire in block <top_level>.

代码如下：

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity i2cmaster is
    Port ( sda : inout  STD_LOGIC;
           scl : out  STD_LOGIC;
           sclclk : in  STD_LOGIC;
           reset : in  STD_LOGIC;
           clk : in  STD_LOGIC;
           dataout : out  STD_LOGIC_VECTOR (7 downto 0);
           resettodivider : out  STD_LOGIC);
end i2cmaster;

architecture Behavioral of i2cmaster is

type state_type is (startstate1, startstate2, sendaddress1, acknowlegde1,  sendinternaladdress, acknowlegde2, startstate3, startstate4, sendaddress2, acknowlegde3, readdata, notacknowlegde, stopstate );
signal current_state : state_type;
signal next_state : state_type :=startstate1;
signal firstaddress: std_logic_vector(7 downto 0);
signal secondaddress: std_logic_vector(7 downto 0);
signal thirdaddress: std_logic_vector(7 downto 0);
signal sendcount: integer range 0 to 7 := 0;
signal temp : std_logic := '0';
signal tempdata : std_logic_vector(7 downto 0):="00000000";

begin

firstaddress<="10101010"; -- Slaveaddress + Writebit
secondaddress<="10101010"; -- Internal Address(first)
thirdaddress<="10101010"; -- Slaveaddress + Readbit


process(current_state, sda, sclclk, temp, sendcount, firstaddress, secondaddress, thirdaddress)
begin
case current_state is

------------------------
    when startstate1 =>
        temp<='0';
        sendcount <=0;
        resettodivider <='1';
        sda<='1';
        next_state <= startstate2;
------------------------        
    when startstate2 =>
        temp<='0';
        sendcount <=0;
        resettodivider <='0';
        sda<='0';   
        if sclclk = '0' then
            next_state <= sendaddress1;
        else
            next_state <= startstate2;      
        end if;     
------------------------        
    when sendaddress1 =>
    resettodivider <='0';

        if sendcount <= 7 then

            if sclclk = '0' and temp='0' then
                sda<=firstaddress(sendcount);
                sendcount <= sendcount + 1;
                temp<='1';
                next_state<=sendaddress1;
            elsif sclclk='1' then
                temp<='0';
                sendcount <=sendcount;
                next_state<=sendaddress1;
            else
                temp<='0';
                sda<='Z';
                sendcount <= sendcount;
                next_state<=sendaddress1;           
            end if;

        else
            temp<='0';
            sendcount <= 0;
            next_state<=acknowlegde1;
        end if;
------------------------            

    when acknowlegde1 =>
    temp<='0';
    resettodivider <='0';
    sendcount <=0;
        if sclclk='1' then
            if sda ='1' then
            next_state<=startstate1;
            else
            next_state<=acknowlegde1;
            end if;
        else
            next_state<=sendinternaladdress;

        end if;
------------------------        
    when sendinternaladdress =>
    resettodivider <='0';
        if sendcount <= 7 then

            if sclclk = '0' and temp='0' then
                sda<=secondaddress(sendcount);
                sendcount<= sendcount + 1;
                temp<='1';
                next_state<=sendinternaladdress;
            elsif sclclk='1' then
                temp<='0';
                sendcount <=sendcount;
                next_state<=sendinternaladdress;
            else
                temp<='0';
                sendcount <= sendcount;
                next_state<=sendinternaladdress;    
                sda<='Z';               
            end if;

        else
            temp<='0';
            sendcount<= 0;
            next_state<=acknowlegde2;
        end if;
------------------------            

    when acknowlegde2 =>
    sendcount <=0;
    temp<='0';
    resettodivider <='0';
        if sclclk='1' then
            if sda ='1' then
            next_state<=startstate1;
            else
            next_state<=acknowlegde2;
            end if;
        else
            next_state<=startstate3;

        end if;
    ------------------------    
    when startstate3 =>
        sendcount <=0;
        temp<='0';
        resettodivider <='1';
        sda<='1';
        next_state <= startstate4;

    ------------------------
    when startstate4 =>
        temp<='0';
        resettodivider <='0';
        sda<='0';   
        sendcount <=0;
        if sclclk = '0' then
            next_state <= sendaddress2;
        else
            next_state <= startstate4;      
        end if;     
    ------------------------
    when sendaddress2 =>
    resettodivider <='0';
        if sendcount <= 7 then
            if sclclk = '0' and temp='0' then
                sda<=thirdaddress(sendcount);
                sendcount<= sendcount + 1;
                temp<='1';
                next_state<=sendaddress2;
            elsif sclclk='1' then
                sendcount<= sendcount;
                temp<='0';
                next_state<=sendaddress2;
            else
                sendcount<= sendcount;
                temp<='0';
                sda<='Z';
                next_state<=sendaddress2;           
            end if;

        else
            temp<='0';
            sendcount <=0;
            next_state<=acknowlegde3;
        end if;

    ------------------------
    when acknowlegde3 =>
    temp<='0';
    sendcount<=0;
    resettodivider <='0';
        if sclclk='1' then
            if sda ='1' then
            next_state<=startstate1;
            else
            next_state<=acknowlegde3;
            end if;
        else
            next_state<=readdata;

        end if;
    ------------------------
    when readdata =>
    resettodivider <='0';
            if sendcount <= 7 then
            if sclclk = '0' and temp='0' then

                tempdata(sendcount)<=sda;
                tempdata<=tempdata;
                sendcount<= sendcount + 1;
                temp<='1';
                next_state<=readdata;
            elsif sclclk='1' then
                tempdata(sendcount)<='0';
                temp<='0';
                sendcount <= sendcount;
                next_state<=readdata;
            else
                temp<='0';
                tempdata(sendcount)<='0';
                sendcount <= sendcount;
                next_state<=readdata;

            end if;

        else
            temp<='0';
            tempdata(sendcount)<='0';
            sendcount <= 0;
            next_state<=notacknowlegde;
        end if;

    ------------------------
    when notacknowlegde =>
    sendcount<=0;
    temp<='0';
    resettodivider <='0';
        if sclclk='0' then
            next_state<=stopstate;
            sda<='Z';
        else
            sda<='1';
            next_state<=notacknowlegde;
        end if;
    ------------------------
    when stopstate =>
        sendcount<=0;
        temp<='0';
        sda<='0';
        resettodivider <='1';
        next_state<=startstate1;

    ------------------------
    when others =>
    sendcount<=0;
    temp<='0';
    resettodivider <='0';
    next_state<=startstate1;
    sda<='Z';
    scl<='Z';
    end case;

end process;

-------

process(clk, reset)
begin
    if (reset='1') then

        current_state <= startstate1;
    elsif rising_edge(clk) then
        current_state <= next_state; 
    end if;
end process;

-------

scl<=sclclk;
dataout<= tempdata;


end Behavioral;

Answer 1

抱怨dead/unused代码

WARNING:Xst:646
  Signal <thirdaddress> is assigned but never used.
  Signal <secondaddress> is assigned but never used.
  Signal <firstaddress> is assigned but never used.

这意味着您的设计中未使用这三个信号。如果您以后不打算使用它们，您可以删除它们 -> 死代码。

有关闩锁的警告 -> 不良设计

WARNING:Xst:736
  Found 1-bit latch for signal <Mtridata_sda> created at line 44.
  Found 1-bit latch for signal <Mtrien_sda> created at line 44.
  Found 3-bit latch for signal <sendcount>.

Latches may be generated from incomplete case or if statements.
We do not recommend the use of latches in FPGA/CPLD designs, as
they may lead to timing problems.

您的状态转换过程不会为每个输入组合分配每个输出信号。这可以通过扩展您的其他案例或通常在案例陈述之前引入默认分配来解决。

关于寄存器的警告，其值不会改变 => 常量内容

WARNING:Xst:1293
  FF/Latch <XLXI_9/sendcount_2> has a constant value of 0 in block <top_level>.
  FF/Latch <XLXI_9/sendcount_1> has a constant value of 0 in block <top_level>.
  FF/Latch <XLXI_9/sendcount_0> has a constant value of 0 in block <top_level>.

This FF/Latch will be trimmed during the optimization process.

您的计数器发送计数已删除。此故障主要是由于：
- FSM 挂断并且不生成计数器的控件
- 计数器处于重置状态
- 计数器没有得到任何 increment/enable 信号

未达到状态警告

WARNING:Xst:1896
  Due to other FF/Latch trimming, FF/Latch <XLXI_9/current_state_FSM_FFd1> has
  a constant value of 0 in block <top_level>.

This FF/Latch will be trimmed during the optimization process.

这是一条传播消息。微调电路一端的寄存器、锁存器和逻辑可能导致另一侧进一步 "optimizations"/微调。

在综合报告中可以找到未达到的状态报告。搜索 'unreached'.

如何解决这些警告？ | VHDL编程

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