WITH - SELECT 具有多个条件的语句 (VHDL)
WITH - SELECT statement with multiple conditions (VHDL)
select VHDL 中在不止一种情况下分配相同信号的语句:
with ALUop select
z <= s_add_sub when "00000",
s_add_sub when "00001",
s_add_sub when "00010",
s_add_sub when "00011",
x AND y when "00100",
x OR y when "00101",
x XOR y when "00110",
lhi when "00111",
seq when "01000",
sne when "01001",
slt when "01010",
sgt when "01011",
sle when "01100",
sge when "01101",
NOT x when "01110",
x when "01111",
shift_out when "10000",
shift_out when "10001",
shift_out when "10010",
y when "10011",
x"00000000" when others;
我如何更改语句以便在多个条件下仅在一行中进行分配,例如:
with ALUop select
z <= s_add_sub when "00000" OR "00001" OR "00010" OR "00011",...
使用 |
而不是 OR
进行多项选择,因此代码如下:
with ALUop select
z <= s_add_sub when "00000" | "00001" | "00010" | "00011",
x AND y when "00100",
...
这类似于 case
的多项选择的语法。
select VHDL 中在不止一种情况下分配相同信号的语句:
with ALUop select
z <= s_add_sub when "00000",
s_add_sub when "00001",
s_add_sub when "00010",
s_add_sub when "00011",
x AND y when "00100",
x OR y when "00101",
x XOR y when "00110",
lhi when "00111",
seq when "01000",
sne when "01001",
slt when "01010",
sgt when "01011",
sle when "01100",
sge when "01101",
NOT x when "01110",
x when "01111",
shift_out when "10000",
shift_out when "10001",
shift_out when "10010",
y when "10011",
x"00000000" when others;
我如何更改语句以便在多个条件下仅在一行中进行分配,例如:
with ALUop select
z <= s_add_sub when "00000" OR "00001" OR "00010" OR "00011",...
使用 |
而不是 OR
进行多项选择,因此代码如下:
with ALUop select
z <= s_add_sub when "00000" | "00001" | "00010" | "00011",
x AND y when "00100",
...
这类似于 case
的多项选择的语法。