映射端口时 Vivado Input/output 违反标准

Question

我正在编写一个要在 Artix-7 Basys 3 FPGA 板上实现的 vhdl 模块。我的设计运行综合和实现成功，但是当我运行写入比特流时，我收到此错误：

[DRC 23-20] Rule violation (NSTD-1) Unspecified I/O Standard - 1 out of 29 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: segt[7].

如您所见，它将 segt 列为问题端口。对于 7 段显示，我将它从 "seg" 重命名为 "segt"，这是它的默认名称，但这并没有阻止错误的发生。它 st运行ge 因为我运行在我的模块中使用默认名称 "sw" 作为开关和 "btnC" 作为按钮时出现此错误。我在 master.xdc 文件中将 "sw" 重命名为 "sw1" 并将 "btnC" 重命名为 "btnC1" 并且我不再收到这些特定端口的错误。任何帮助将不胜感激。

这是主要模块：

entity timer_test is
    port(
    clk: in std_logic;
    btnC1: in std_logic;
    an: out std_logic_vector(3 downto 0);
    segt: out std_logic_vector(7 downto 0);
    led: out std_logic_vector(15 downto 0);
    sw1: in std_logic_vector(15 downto 0)
    );
end timer_test;

architecture arch of timer_test is
    signal d3,d2, d1, d0: std_logic_vector(3 downto 0);
    signal one_sec: std_logic;
begin
    disp_unit: entity work.disp_hex_mux
      port map(
         clk=>clk, reset=>'0',
         hex3=>d3, hex2=>d2, hex1=>d1, hex0=>d0,
         dp_in=>"1101", an=>an, sseg=>segt);

    divider_unit: entity work.clock_divider
        port map(
            clk=>clk,
            start=>'1',
            onesec=>one_sec);

    counter_unit: entity work.count_down_timer
        port map(
            min_in(7 downto 0)=>sw1(15 downto 8),
            sec_in(7 downto 0)=>sw1(7 downto 0),
            clk=>clk,
            one_sec=>one_sec,
            reset=>btnC1,
            d3=>d3 ,d2 =>d2, d1=>d1, d0=>d0,
            led=>led);
end arch;

Master.xdc的相关部分：

## Clock signal
set_property PACKAGE_PIN W5 [get_ports clk]                         
    set_property IOSTANDARD LVCMOS33 [get_ports clk]
    create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk]

## Switches
set_property PACKAGE_PIN V17 [get_ports {sw1[0]}]                   
    set_property IOSTANDARD LVCMOS33 [get_ports {sw1[0]}]
set_property PACKAGE_PIN V16 [get_ports {sw1[1]}]                   
    set_property IOSTANDARD LVCMOS33 [get_ports {sw1[1]}]
set_property PACKAGE_PIN W16 [get_ports {sw1[2]}]                   
    set_property IOSTANDARD LVCMOS33 [get_ports {sw1[2]}]
set_property PACKAGE_PIN W17 [get_ports {sw1[3]}]                   
    set_property IOSTANDARD LVCMOS33 [get_ports {sw1[3]}]
set_property PACKAGE_PIN W15 [get_ports {sw1[4]}]                   
    set_property IOSTANDARD LVCMOS33 [get_ports {sw1[4]}]
set_property PACKAGE_PIN V15 [get_ports {sw1[5]}]                   
    set_property IOSTANDARD LVCMOS33 [get_ports {sw1[5]}]
set_property PACKAGE_PIN W14 [get_ports {sw1[6]}]                   
    set_property IOSTANDARD LVCMOS33 [get_ports {sw1[6]}]
set_property PACKAGE_PIN W13 [get_ports {sw1[7]}]                   
    set_property IOSTANDARD LVCMOS33 [get_ports {sw1[7]}]
set_property PACKAGE_PIN V2 [get_ports {sw1[8]}]                    
    set_property IOSTANDARD LVCMOS33 [get_ports {sw1[8]}]
set_property PACKAGE_PIN T3 [get_ports {sw1[9]}]                    
    set_property IOSTANDARD LVCMOS33 [get_ports {sw1[9]}]
set_property PACKAGE_PIN T2 [get_ports {sw1[10]}]                   
    set_property IOSTANDARD LVCMOS33 [get_ports {sw1[10]}]
set_property PACKAGE_PIN R3 [get_ports {sw1[11]}]                   
    set_property IOSTANDARD LVCMOS33 [get_ports {sw1[11]}]
set_property PACKAGE_PIN W2 [get_ports {sw1[12]}]                   
    set_property IOSTANDARD LVCMOS33 [get_ports {sw1[12]}]
set_property PACKAGE_PIN U1 [get_ports {sw1[13]}]                   
    set_property IOSTANDARD LVCMOS33 [get_ports {sw1[13]}]
set_property PACKAGE_PIN T1 [get_ports {sw1[14]}]                   
    set_property IOSTANDARD LVCMOS33 [get_ports {sw1[14]}]
set_property PACKAGE_PIN R2 [get_ports {sw1[15]}]                   
    set_property IOSTANDARD LVCMOS33 [get_ports {sw1[15]}]


## LEDs
set_property PACKAGE_PIN U16 [get_ports {led[0]}]                   
    set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}]
set_property PACKAGE_PIN E19 [get_ports {led[1]}]                   
    set_property IOSTANDARD LVCMOS33 [get_ports {led[1]}]
set_property PACKAGE_PIN U19 [get_ports {led[2]}]                   
    set_property IOSTANDARD LVCMOS33 [get_ports {led[2]}]
set_property PACKAGE_PIN V19 [get_ports {led[3]}]                   
    set_property IOSTANDARD LVCMOS33 [get_ports {led[3]}]
set_property PACKAGE_PIN W18 [get_ports {led[4]}]                   
    set_property IOSTANDARD LVCMOS33 [get_ports {led[4]}]
set_property PACKAGE_PIN U15 [get_ports {led[5]}]                   
    set_property IOSTANDARD LVCMOS33 [get_ports {led[5]}]
set_property PACKAGE_PIN U14 [get_ports {led[6]}]                   
    set_property IOSTANDARD LVCMOS33 [get_ports {led[6]}]
set_property PACKAGE_PIN V14 [get_ports {led[7]}]                   
    set_property IOSTANDARD LVCMOS33 [get_ports {led[7]}]
set_property PACKAGE_PIN V13 [get_ports {led[8]}]                   
    set_property IOSTANDARD LVCMOS33 [get_ports {led[8]}]
set_property PACKAGE_PIN V3 [get_ports {led[9]}]                    
    set_property IOSTANDARD LVCMOS33 [get_ports {led[9]}]
set_property PACKAGE_PIN W3 [get_ports {led[10]}]                   
    set_property IOSTANDARD LVCMOS33 [get_ports {led[10]}]
set_property PACKAGE_PIN U3 [get_ports {led[11]}]                   
    set_property IOSTANDARD LVCMOS33 [get_ports {led[11]}]
set_property PACKAGE_PIN P3 [get_ports {led[12]}]                   
    set_property IOSTANDARD LVCMOS33 [get_ports {led[12]}]
set_property PACKAGE_PIN N3 [get_ports {led[13]}]                   
    set_property IOSTANDARD LVCMOS33 [get_ports {led[13]}]
set_property PACKAGE_PIN P1 [get_ports {led[14]}]                   
    set_property IOSTANDARD LVCMOS33 [get_ports {led[14]}]
set_property PACKAGE_PIN L1 [get_ports {led[15]}]                   
    set_property IOSTANDARD LVCMOS33 [get_ports {led[15]}]


#7 segment display
set_property PACKAGE_PIN W7 [get_ports {segt[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {segt[6]}]
set_property PACKAGE_PIN W6 [get_ports {segt[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {segt[5]}]
set_property PACKAGE_PIN U8 [get_ports {segt[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {segt[4]}]
set_property PACKAGE_PIN V8 [get_ports {segt[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {segt[3]}]
set_property PACKAGE_PIN U5 [get_ports {segt[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {segt[2]}]
set_property PACKAGE_PIN V5 [get_ports {segt[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {segt[1]}]
set_property PACKAGE_PIN U7 [get_ports {segt[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {segt[0]}]

set_property PACKAGE_PIN V7 [get_ports dp]                          
    set_property IOSTANDARD LVCMOS33 [get_ports dp]

set_property PACKAGE_PIN U2 [get_ports {an[0]}]                 
    set_property IOSTANDARD LVCMOS33 [get_ports {an[0]}]
set_property PACKAGE_PIN U4 [get_ports {an[1]}]                 
    set_property IOSTANDARD LVCMOS33 [get_ports {an[1]}]
set_property PACKAGE_PIN V4 [get_ports {an[2]}]                 
    set_property IOSTANDARD LVCMOS33 [get_ports {an[2]}]
set_property PACKAGE_PIN W4 [get_ports {an[3]}]                 
    set_property IOSTANDARD LVCMOS33 [get_ports {an[3]}]


##Buttons
set_property PACKAGE_PIN U18 [get_ports btnC1]                      
    set_property IOSTANDARD LVCMOS33 [get_ports btnC1]

如何解决这些违规问题？

Answer 1

错误消息明确指出 29 个端口中只有 1 个受到影响，因此这告诉我们我们只是在寻找一个有问题的引脚。错误消息的末尾指定 segt[7]。您对 segt 的声明如下：

segt: out std_logic_vector(7 downto 0);

请记住，在 VHDL 中，downto 是 包含的 。这意味着 segt 有 8 个元素。

现在查看您的约束文件：没有为 segt[7] 指定的 IO 标准。您只包含 segt[6] 到 segt[0]，其中 none 包含在您的错误中。只需添加segt[7]的IO标准规范：

set_property PACKAGE_PIN <pin> [get_ports {segt[7]}]
    set_property IOSTANDARD LVCMOS33 [get_ports {segt[7]}]

映射端口时 Vivado Input/output 违反标准

Vivado Input/output standard violation when mapping ports

hardware

fpga

vhdl