使用 Icestorm 分析比特流

Analyzing bitstreams using Icestorm

我正在尝试理解 Yosys/arachne-pnr 生成的比特流,如 http://www.clifford.at/icestorm/ 中所述:

The recommended approach for learning how to use this documentation is to synthesize very simple circuits using Yosys and Arachne-pnr, run the icestorm tool icebox_explain on the resulting bitstream files, and analyze the results using the HTML export of the database mentioned above. icebox_vlog can be used to convert the bitstream to Verilog. The output file of this tool will also outline the signal paths in comments added to the generated Verilog code.

为了理解比特流变化的影响,如果我可以改变 .ex 文件并将其转换回 ASCII 比特流(而不是必须手动识别比特),那将会很有帮助) 上传到 FPGA。有办法吗?

我有点担心无效比特流会损坏 FPGA。是否存在已知会发生这种情况的情况?有没有办法模拟比特流?

此外,拥有某种“更高级别”的解释格式会很有帮助,例如显示 I/O 块上的 IE/REN 位,它们对应于它们,而不是它们必须在比特流中设置的块。有这样的格式吗?

我知道生成等效 Verilog 电路的可能性,但问题是它通常不允许我无损往返返回比特流。有没有一种方法可以生成等效的 Verilog 电路(例如,通过显式实例化块)在使用 Yosys/arachne-pnr 处理时产生完全相同的比特流?

I'm a bit concerned about damaging the FPGA with an invalid bitstream. Are there situations where this is known to happen? Is there a way to simulate a bitstream?

到目前为止我还没有损坏任何FPGA。 (然而,在 运行 进行了一些循环重新编程的测试后,我设法损坏了一个冰棒上的串行闪存。)

但这并不意味着您不能通过使用无效比特流对 FPGA 进行编程来损坏它。理论上,您可以以产生驱动程序冲突的方式配置 FPGA。我不知道硬件如何处理类似的事情。我没有 运行 任何实验来找出答案..

Also, it would be helpful to have some kind of “higher-level” explanation format which e.g. shows the IE/REN bits on the I/O blocks to which they correspond, not the one on which they have to be set in the bitstream. Is there such a format?

icebox_vlog 产生更高级别的输出。但它不会输出 I/O 块之类的东西,因此它可能对您的需求来说太高级了。

I know of the possibility to generate an equivalent Verilog circuit, but the problem with this is that it doesn't usually allow me a lossless round-trip back into a bitstream. Is there a way to generate an equivalent Verilog circuit which (e.g. by instantiating the blocks explicitly) yields the exact same bitstream when processed with Yosys/arachne-pnr?

暂时没有。但扩展 icebox_vlog 以提供此功能应该不会太难。所以如果你真的需要它,它可能是你可以自己添加的东西。