为什么 ADD 在 Z80 上是 4 个周期？
Why ADD is 4 cycles on Z80?
我用这个ALU框图作为学习material：http://www.righto.com/2013/09/the-z-80-has-4-bit-alu-heres-how-it.html
我不熟悉电子产品。我目前认为需要一个时钟周期来将数据从寄存器或锁存器移动到另一个寄存器或锁存器，最终通过逻辑门网络。
所以这是我对 ADD 发生的事情的理解：
- 周期 1：将寄存器移动到内部锁存器
- 周期 2：将低半字节内部锁存器移动到内部结果锁存器（通过 ALU）
- 第 3 周期，并行：
- 将高半字节内部锁存器移动到目标寄存器（通过 ALU）
- 将内部结果锁存器移至寄存器
我认为操作周期 3 是并行完成的，因为有两个 4 位总线（用于高半字节和低半字节）并且寄存器总线似乎是 8 位。
The PC is placed on the address bus at the beginning of the M1 cycle.
One half clock cycle later the MREQ signal goes active. At this time
the address to the memory has had time to stabilize so that the
falling edge of MREQ can be used directly as a chip enable clock to
dynamic memories. The RD line also goes active to indicate that the
memory read data should be enabled onto the CPU data bus. The CPU
samples the data from the memory on the data bus with the rising edge
of the clock of state T3 and this same edge is used by the CPU to turn
off the RD and MREQ signals. Thus, the data has already been sampled
by the CPU before the RD signal becomes inactive. Clock state T3 and
T4 of a fetch cycle are used to refresh dynamic memories. The CPU uses
this time to decode and execute the fetched instruction so that no
other operation could be performed at this time.
因此，它似乎主要是关于内存接口以读取操作码，而不是实际执行加法 — 解码和执行完全发生在时钟状态 T3 和 T4 内。鉴于 z80 has a 4-bit ALU，执行 8 位加法需要两次操作。这可能解释了两个循环的使用。
我用这个ALU框图作为学习material：http://www.righto.com/2013/09/the-z-80-has-4-bit-alu-heres-how-it.html
我不熟悉电子产品。我目前认为需要一个时钟周期来将数据从寄存器或锁存器移动到另一个寄存器或锁存器，最终通过逻辑门网络。
所以这是我对 ADD 发生的事情的理解：
- 周期 1：将寄存器移动到内部锁存器
- 周期 2：将低半字节内部锁存器移动到内部结果锁存器（通过 ALU）
- 第 3 周期，并行：
- 将高半字节内部锁存器移动到目标寄存器（通过 ALU）
- 将内部结果锁存器移至寄存器
我认为操作周期 3 是并行完成的，因为有两个 4 位总线（用于高半字节和低半字节）并且寄存器总线似乎是 8 位。
The PC is placed on the address bus at the beginning of the M1 cycle. One half clock cycle later the MREQ signal goes active. At this time the address to the memory has had time to stabilize so that the falling edge of MREQ can be used directly as a chip enable clock to dynamic memories. The RD line also goes active to indicate that the memory read data should be enabled onto the CPU data bus. The CPU samples the data from the memory on the data bus with the rising edge of the clock of state T3 and this same edge is used by the CPU to turn off the RD and MREQ signals. Thus, the data has already been sampled by the CPU before the RD signal becomes inactive. Clock state T3 and T4 of a fetch cycle are used to refresh dynamic memories. The CPU uses this time to decode and execute the fetched instruction so that no other operation could be performed at this time.
因此，它似乎主要是关于内存接口以读取操作码，而不是实际执行加法 — 解码和执行完全发生在时钟状态 T3 和 T4 内。鉴于 z80 has a 4-bit ALU，执行 8 位加法需要两次操作。这可能解释了两个循环的使用。