vivado 在处理来自输出的 X 波形时遇到问题，获取一个数组并在 7 段 LED 计数器有限状态机上制作它的波形

Question

我正在尝试创建一个 7 段 LED 计数器，我遇到的两个问题是 a 到 g 在模拟波形中仅显示为 X，我不知道如何获取当前状态的 q并使其波形到测试台。我认为这类似于在名为 Q2、Q1 和 Q0 的测试台中创建电线并将它们添加为 .q[2] (Q2) 等等，但它似乎并不喜欢那样。我对此很陌生，所以它可能非常简单。谢谢！

`timescale 1ns / 1ps

//inputs, outputs

module Counter(
input u,
input clrn,
input clk,
output reg a,
output reg b,
output reg c,
output reg d,
output reg e,
output reg f,
output reg g);

reg [2:0] ns; //next state
reg [2:0] q; //present state
//declaration of the states    
parameter [2:0] S0 = 3'b000, S1 = 3'b001, S2 = 3'b010, S3 = 3'b011, S4 = 3'b100, S5 = 3'b101;

always @ (negedge clk or posedge clrn)
begin
if(clrn) //if reset present state q goes to 0
    q = S0;
else
begin
    case(q) //tests present state
        S0:
        if (u==1) begin
            ns = S1;
            a = 1'b0;
            b = 1'b1;
            c = 1'b1;
            d = 1'b0;
            e = 1'b0;
            f = 1'b0;
            g = 1'b0;
        end
        else begin
            ns = S5;
            a = 1'b1;
            b = 1'b0;
            c = 1'b1;
            d = 1'b1;
            e = 1'b0;
            f = 1'b1;
            g = 1'b1;
        end

        S1:
        if (u==1) begin
            ns = S2;
            a = 1'b1;
            b = 1'b1;
            c = 1'b0;
            d = 1'b1;
            e = 1'b1;
            f = 1'b0;
            g = 1'b1;
        end
        else begin
            ns = S0;
            a = 1'b1;
            b = 1'b1;
            c = 1'b1;
            d = 1'b1;
            e = 1'b1;
            f = 1'b1;
            g = 1'b0;
        end

        S2:
        if (u==1) begin
            ns = S3;
            a = 1'b1;
            b = 1'b1;
            c = 1'b1;
            d = 1'b1;
            e = 1'b0;
            f = 1'b0;
            g = 1'b1;
        end
        else begin
            ns = S1;
            a = 1'b0;
            b = 1'b1;
            c = 1'b1;
            d = 1'b0;
            e = 1'b0;
            f = 1'b0;
            g = 1'b0;
        end            

        S3:
        if (u==1) begin
            ns = S4;
            a = 1'b0;
            b = 1'b1;
            c = 1'b1;
            d = 1'b0;
            e = 1'b0;
            f = 1'b1;
            g = 1'b1;
        end
        else begin
            ns = S2;
            a = 1'b1;
            b = 1'b0;
            c = 1'b1;
            d = 1'b1;
            e = 1'b0;
            f = 1'b1;
            g = 1'b1;
        end   

        S4:
        if (u==1) begin
            ns = S5;
            a = 1'b1;
            b = 1'b0;
            c = 1'b1;
            d = 1'b1;
            e = 1'b0;
            f = 1'b1;
            g = 1'b1;
        end
        else begin
            ns = S3;
            a = 1'b1;
            b = 1'b1;
            c = 1'b1;
            d = 1'b1;
            e = 1'b0;
            f = 1'b0;
            g = 1'b1;
        end

        S5:
        if (u==1) begin
            ns = S0;
            a = 1'b1;
            b = 1'b1;
            c = 1'b1;
            d = 1'b1;
            e = 1'b1;
            f = 1'b1;
            g = 1'b0;
        end
        else begin
            ns = S4;
            a = 1'b0;
            b = 1'b1;
            c = 1'b1;
            d = 1'b0;
            e = 1'b0;
            f = 1'b1;
            g = 1'b1;
        end

    endcase

    q = ns;

end

end

endmodule

测试平台：

`timescale 1ns / 1ps


module testbench;

reg U, CLK, CLRN;
wire A, B, C, D, E, F, G;

Counter inst(

.clk (CLK),
.u (U),
.clrn (CLRN),
.a (A),
.b (B),
.c (C),
.d (D),
.e (E),
.f (F),
.g (G));

initial

begin //CLRN starts low, CLK starts high, U starts high

CLRN = 1'b0;

CLK = 1'b1;

U = 1'b1;

//CLK will change every ns

#1 CLRN = 1'b1;
CLK = 1'b0;

#1 CLK = 1'b1;

#1 CLK = 1'b0;

#1 CLK = 1'b1;

#1 CLK = 1'b0;

#1 CLK = 1'b1;

#1 CLK = 1'b0;

#1 CLK = 1'b1;

#1 CLK = 1'b0;

#1 CLK = 1'b1;

#1 CLK = 1'b0;

#1 CLK = 1'b1;

#1 CLK = 1'b0;

#1 CLK = 1'b1;

#1 CLK = 1'b0;

#1 CLK = 1'b1;

#1 CLK = 1'b0; //On the ns 17 u will change to low
U = 1'b0;

#1 CLK = 1'b1;

#1 CLK = 1'b0;

#1 CLK = 1'b1;

#1 CLK = 1'b0;

#1 CLK = 1'b1;

#1 CLK = 1'b0;

#1 CLK = 1'b1;

#1 CLK = 1'b0;

#1 CLK = 1'b1;

#1 CLK = 1'b0;

#1 CLK = 1'b1;

#1 CLK = 1'b0;

#1 CLK = 1'b1;

#1 CLK = 1'b0;

#1 CLK = 1'b1;

#1 CLK = 1'b0;

#1 CLK = 1'b1;

#1 CLK = 1'b0;

#1 CLK = 1'b1;

#1 CLK = 1'b0;

#1 CLK = 1'b1;

#1 CLK = 1'b0;

#1 CLK = 1'b1;

end

endmodule

Answer 1

参考这些来源将信号添加到波形：

1- https://cseweb.ucsd.edu/classes/wi11/cse141L/tipsandtricks.html

2- https://forums.xilinx.com/t5/Simulation-and-Verification/Viewing-internal-signal-waveforms-in-ISIM/td-p/244736

3- ug937-vivado-design-suite-simulation-tutorial

也考虑看看Xilinx模板代码，我觉得你的编码风格不规范。（模拟和状态机）

Answer 2

您有两个主要问题需要解决。

你有一个 CLRn，但你说 if(clrn)。负极性复位你需要一个if (~clrn)
您在 always 语句中的重置正在寻找敏感列表中的上升沿转换。你至少需要在 clrn 上有一个 negedge 敏感度，就像这样...

always @ (negedge clk or negedge clrn)

但我会推荐以下更标准的正时钟边沿灵敏度......

always @ (posedge clk or negedge clrn)

vivado 在处理来自输出的 X 波形时遇到问题，获取一个数组并在 7 段 LED 计数器有限状态机上制作它的波形

vivado having trouble with X waveform from outputs, taking an array and making it waveform on a 7 segment led counter finite state machine

verilog

xilinx

vivado