由于 verilog 与 verilator 中的无符号算术错误,比较是恒定的

Comparison is constant due to unsigned arithmetic error in verilog with verilator

我正在使用以下逻辑在 Verilog 的双峰预测器中实现 2 位饱和计数器,并且我还在使用 verilator,如下所示:

• For each branch, maintain a 2-bit saturating counter:
-if the branch is taken: counter = min(3,counter+1)
-if the branch is not taken: counter = max(0,counter-1)
• If (counter >= 2), predict taken, else predict not taken

module Bimodal(
input clk,
input reset,
input taken, //from ALU unit in execute stage
input branch, //from control unit in decode stage
input [31:0] instrAddr, // current address taken from fetch/decode stage
output reg predicted_taken_or_not);

reg [1:0] saturating_counter [0:1023];


integer i;
parameter max_val = 3 ;
parameter min_val = 0 ;

assign predicted_taken_or_not = saturating_counter[instrAddr[11:2]]>= 2'd2 && branch? 1'd1 : 1'd0;


// write ports to update the 2-bit saturating counter
always @(posedge clk) begin

if(reset) begin
 for(int i=0; i<1024; i++) begin
    saturating_counter[i] = 2'd1;
 end
end

else if (taken) begin
if(max_val>saturating_counter[instrAddr[11:2]]+1)
    saturating_counter[instrAddr[11:2]]<=saturating_counter[instrAddr[11:2]]+1;
else
    saturating_counter[instrAddr[11:2]]<=max_val;
end

else if (~taken) begin
if(min_val>saturating_counter[instrAddr[11:2]]-1)
   saturating_counter[instrAddr[11:2]]<=min_val;
else
    saturating_counter[instrAddr[11:2]]<=saturating_counter[instrAddr[11:2]]-1;
end

end

endmodule

但我收到以下错误

%Warning-UNSIGNED: Bimodal.v:36: Comparison is constant due to unsigned arithmetic
%Warning-UNSIGNED: Use "/* verilator lint_off UNSIGNED */" and lint_on around source to disable this message.
%Error: Exiting due to 1 warning(s)
%Error: Command Failed /home/verilator-3.884/verilator_bin -O4 --cc MIPS.v --exe sim_main.cpp

我做错了什么吗?

您的编译器当前设置为在出现某些警告时失败。问题的根源可能是您的 min_val 参数当前为 0。同时,您只检查 min_val(除非您在某处覆盖参数,否则它始终为 0)是否大于RHS(右侧)上没有符号的 2 位值。这意味着它永远不会是负数。

Is 0 > 0 ?  No
Is 0 > 1 ?  No
is 0 > 2 ?  No
Is 0 > 3 ?  No

答案始终是否定的,因此根据警告结果是不变的。

您希望测试

Is 0 > 0 ? No
Is 0 > 1 ? No
Is 0 > -2 ? Yes
Is 0 > -1 ? Yes

如果需要,您可能需要更改您的逻辑类型,或更改您的比较。

请记住,verilog 中的 regs 是无符号值,无论您分配给 reg 的是正无符号值。您与零进行比较的所有非正弦值都将大于或等于零。如果你想要一个带符号的比较,你可以使用 $signed() 指令。

if(min_val>$signed(saturating_counter[instrAddr[11:2]]-1))