具有多个 SystemC 模拟的项目导致异常

Question

在我的项目中有几个函数执行 SystemC 模拟（每个函数都有自己的声明前奏和sc_start()）。

所以它们的构造如下：

// first Simulation:
sc_signal<double> s1_sim1;
..
ControlFoo<double> *cf = new ControlFoo<double>();
cf->Foo_port(s1_sim1);
..
sc_start(); // works fine
delete(cf);
..
// second Simulation:
sc_signal<double> s1_sim2; // this leads to an exception

第一个模拟按预期运行，直到 sc_stop()。但是当我在第一次模拟完成后尝试声明新的 sc_signal 时，它会抛出异常。

如何避免这种情况？

Answer 1

用户指南："You can only start a simulation after you instantiate and properly connect all modules and signals."

如何动态创建硬件？

选项是将模型拆分为单独的项目或在一个项目中声明所有模型，并有一种打开和关闭它们的方法，例如 'enable' 信号

在回答你的后续问题时，你可以尝试这样的事情。我们创建了一个具有 "enable" 输出的控制器模块，我们使用它们来控制 3 个受控模块，我们在这里使用这些模块来表示我们希望打开和关闭的一些模型或子系统。

#include <systemc.h>
#include <iostream>

using namespace sc_core;
using namespace std;

/*
 Controller module with output enable signals to enable and 
 disable other modules representing the models we wish to switch on/off
*/
SC_MODULE(Controller){

    SC_CTOR(Controller) 
        : clk_i("clk_i"), 
        en_a("en_a"), 
        en_b("en_b"),
        en_c("en_c"),
        counter(0)
    {
        SC_METHOD(proc);
        sensitive << clk_i.pos(); //run process on positive clock edge
    }

    void proc(){
        if(counter < 10){ //enable model A and disable others
            en_a.write(true);
            en_b.write(false);
            en_c.write(false);
        }
        else if(counter < 20){ //enable B and disable others
            en_a.write(false);
            en_b.write(true);
            en_c.write(false);
        }
        else{ //enable C and disable others
            en_a.write(false);
            en_b.write(false);
            en_c.write(true);
        }
        counter = (counter + 1) % 30; 
    }

    sc_in<bool> clk_i; // clock input
    sc_out<bool> en_a; // enable model A when high
    sc_out<bool> en_b; // enable model B when high
    sc_out<bool> en_c; // enable model C when high
    int counter; //simple counter to simulate some condition
};

/*
 Module with an enable signal to represent the sub-systems we 
 wish to switch on and off
*/
SC_MODULE(Controlled){
    SC_CTOR(Controlled) : en_i("en_i"), clk_i("clk_i"){
        SC_METHOD(proc);
        sensitive << clk_i.pos(); //run process on positive clock edge
    }

    void proc(){
        //if we are enabled then run "real process" otherwise do nothing
        if(en_i.read() == true) enabledProc();

    }

    // the "real process" that we wish to switch on and off
    void enabledProc(){
        cout << "model " << name() << " is enabled\n";
    }

    sc_in<bool> en_i;
    sc_in<bool> clk_i;
};


int sc_main(int, char**){

    // created controller and 3 controlled modules
    Controller controller("controller");
    Controlled modelA("A"), modelB("B"), modelC("C");

    // create a clock and connect it to all 4 modules
    sc_clock clk("clk", 1.0, SC_SEC);
    controller.clk_i(clk);
    modelA.clk_i(clk);
    modelB.clk_i(clk);
    modelC.clk_i(clk);

    // create an enable signal for each module and connect to controller
    sc_signal<bool> en_a("en_a");
    sc_signal<bool> en_b("en_b");
    sc_signal<bool> en_c("en_c");
    controller.en_a(en_a);
    controller.en_b(en_b);
    controller.en_c(en_c);
    // connect enable lines to controlled modules
    modelA.en_i(en_a);
    modelB.en_i(en_b);
    modelC.en_i(en_c);

    sc_start(30, SC_SEC); // run for 30 seconds

    return 0;
}

你应该得到输出

model A is enabled
model A is enabled
model A is enabled
model A is enabled
model A is enabled
model A is enabled
model A is enabled
model A is enabled
model A is enabled
model A is enabled
model B is enabled
model B is enabled
model B is enabled
model B is enabled
model B is enabled
model B is enabled
model B is enabled
model B is enabled
model B is enabled
model B is enabled
model C is enabled
model C is enabled
model C is enabled
model C is enabled
model C is enabled
model C is enabled
model C is enabled
model C is enabled
model C is enabled
model C is enabled

随着控制器依次启用和禁用每个模块。这个简单的示例应该可以帮助您入门，直到您最终可以用您的真实系统替换我的简单打印系统

具有多个 SystemC 模拟的项目导致异常

Project with multiple SystemC Simulations leads to an exception

c++

simulation

systemc