VHDL error: type specified in Qualified Expression must match type implied for expression by context

Question

我正在尝试使用自己创建的函数（这是我第一次尝试，所以我可能在那里做错了）。

当我尝试编译时收到以下错误消息：错误 (13815)：Averageador.vhd(38) 处的 VHDL 限定表达式错误：限定表达式中指定的除法类型必须匹配隐含的无符号类型按上下文表达

除法是我函数的名称。此函数将任何 16 位无符号值除以未知无符号值，并将结果作为定点 32 位无符号值给出，其中 16 位在点的每一侧。这是代码：

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;

package propios is

 --function declaration.
function divide (a : UNSIGNED; b: UNSIGNED) return UNSIGNED;
end propios;   --end of package.

package body propios is  --start of package body
--definition of function
function  divide (a : UNSIGNED; b: UNSIGNED) return UNSIGNED is
variable a_int : unsigned(a'length+7 downto 0):= (others => '0');
variable b_int : unsigned(b'length-1 downto 0):=b;
variable r : unsigned(b'length downto 0):= (others => '0');
variable q : unsigned(31 downto 0):= (others => '0');
begin
a_int(a'length+7 downto 16):=a;
for i in a'length+7 downto 0 loop
    r(b'length downto 1):=r(b'length-1 downto 0);
    r(0) := a_int(i);
    if (r>=q) then
        r:=r-b_int;
        q(i):='1';
    end if;
end loop;
return q;
end divide;
--end function
end propios;  --end of the package body

I return q 是一个 32 位无符号数。

这是我使用函数并提示错误信息的一段代码：

   library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

library work;
use work.propios.all;

ENTITY test IS --Con alimentación de datos posición a posición, no vector de golpe.

END test;
Architecture simple of test is
signal a:unsigned(15 downto 0);
signal b:unsigned(13 downto 0);
signal c: unsigned(31 downto 0);
begin


process 
begin
a<="1100100110100111";
b<="00000000000010";
c<= divide(a,b);


end process;


end simple;

有什么建议吗？谢谢

Answer 1

问题是（如user1155120所说）由于在包上使用了包std_logic_arith，在测试中使用了numeric_std。因此，即使两者都称为 unsigned，它们也不兼容。

两个代码都包含其他错误，这些错误也已更正但与第一个错误无关。

这是一个带有将2个无符号数除以逗号后16位的函数的包：

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

package propios is

 --function declaration.
function divide (a : UNSIGNED; b: UNSIGNED) return UNSIGNED;
end propios;   --end of package.

package body propios is  --start of package body
--definition of function
function  divide (a : UNSIGNED; b: UNSIGNED) return UNSIGNED is
variable a_int : unsigned(a'length+15 downto 0):= (others => '0');--Length is 16 bit longer than a
variable b_int : unsigned(b'length-1 downto 0):=b;
variable r : unsigned(b'length downto 0):= (others => '0');
variable q : unsigned(a'length+15 downto 0):= (others => '0');--Same length as a_int
variable i: natural;

begin
a_int(a'length+15 downto 16):=a;--the MSBits are "a" and the rest will be 0's
for i in a'length+15 downto 0 loop--division using a modified version of integer division (unsigned) with remainder as seen in:
--https://en.wikipedia.org/wiki/Division_algorithm
    r(b'length downto 1):=r(b'length-1 downto 0);
    r(0) := a_int(i);
    if (r>=b_int) then
        r:=r-b_int;
        q(i):='1';
    end if;
end loop;
return q;
end divide;
--end function
end propios;  --end of the package body

这是检查其功能的简单测试：

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

library work;
use work.propios.all;

ENTITY test IS --Con alimentación de datos posición a posición, no vector de golpe.

END test;
Architecture simple of test is
signal a:unsigned(23 downto 0);
signal b:unsigned(13 downto 0);
signal c: unsigned(39 downto 0);
begin


process 
begin
a<="000000001100100110100111";
b<="00000000010010";
wait for 200ps;
c<= divide (a , b);

wait;   
end process;


end simple;

要检查结果，请记住结果的最后 16 位在定点后面。

VHDL error: type specified in Qualified Expression must match type implied for expression by context

VHDL error: type specified in Qualified Expression must match type implied for expression by context

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