Errors:TopLevel Modelsim 上的 vhdl

Question

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL; 
entity TopLevel is
Port ( reset : in std_logic;
clock : in std_logic;
coin : in std_logic;
push : in std_logic;
count1 : out std_logic_vector(15 downto 0)

); 
end TopLevel;
architecture Modular of TurnstileDetector is
signal unlock : std_logic;
begin
controller: entity   TurnstileDetectorController
Port map ( reset => reset,
clock => clock,
coin => coin,
push => push,
unlock => unlock 
);
counter: entity work.counter
Port map ( reset => reset,
clock => clock,
cen => unlock,
q => count1
);
end architecture Modular;

错误： ** 错误：(vcom-11) 找不到 work.turnstiledetector.

** 错误：C:/Modeltech_pe_edu_10.4a/examples/TopLevel.vhd(14): VHDL 编译器正在退出

Answer 1

您需要将 architecture Modular of TurnstileDetector is 更改为 architecture Modular of TopLevel is

Errors:TopLevel Modelsim 上的 vhdl

Errors:TopLevel vhdl on Modelsim

vhdl

modelsim