VHDL-"Net pwr is constantly driven"
VHDL - "Net pwr is constantly driven"
我正在尝试学习 VHDL，作为练习，我正在尝试构建一个使用 RS-232 样式信号（8N1 格式）的非常简单的串行端口。
这是小项目中两个 vhdl 文件的代码...
"glue.vhd"...（顶级模块）
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use ieee.std_logic_unsigned.all;
library MACHXO2;
use MACHXO2.components.all;
entity Glue is
port(
tx : out std_logic := '1' --idle high
);
end entity Glue;
architecture behavioural of Glue is
SIGNAL clk : STD_LOGIC;
signal divider : std_logic_vector(23 downto 0);
--internal oscillator
COMPONENT OSCH
GENERIC(
NOM_FREQ: string
);
PORT(
STDBY : IN STD_LOGIC;
OSC : OUT STD_LOGIC;
SEDSTDBY : OUT STD_LOGIC);
END COMPONENT;
begin
--internal oscillator
OSCInst0: OSCH
GENERIC MAP (NOM_FREQ => "3.69")
PORT MAP (STDBY => '0', OSC => clk, SEDSTDBY => OPEN);
ser : entity SerialTX
port map (baud_clk => divider(5),
byte_to_transmit => "00101001",
transmit_now => divider(16),
busy => OPEN,
serial_out => tx);
clocker : process (clk)
begin
IF(clk'event and clk='1') then
divider <= divider + 1;
END IF;
end process clocker;
end architecture behavioural;
SerialTX.vhd...（由 glue.vhd 调用）
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity SerialTX is
port (
baud_clk : in std_logic;
byte_to_transmit : in std_ulogic_vector(7 downto 0); --the byte that we want to transmit
transmit_now : in std_logic; --a rising edge causes the byte to be sent out
busy : out std_logic; --wait for this to go low before transmiting more data
serial_out : out std_logic --the RS232 serial signal
);
end SerialTX;
architecture behavioural of SerialTX is
signal bit_buf : unsigned(9 downto 0); --(STOP bit) & (8 data bits) & (START bit)
signal internal_busy : std_logic := '0';
begin
busy <= internal_busy;
initialise_transmit : process(transmit_now, internal_busy) is
begin
if(transmit_now'event and (transmit_now = '1')) then
if((internal_busy = '0')) then
internal_busy <= '1'; --causes the "transmit_bits" process below to begin shifting out bits
bit_buf <= unsigned('1' & byte_to_transmit & '0'); --latch in the byte to our internal copy
end if;
end if;
end process initialise_transmit;
transmit_bits : process(internal_busy, baud_clk) is
variable bit_counter : integer range 0 to 10 := 0;
begin
if(baud_clk'event and (baud_clk = '1')) then
if(internal_busy = '1') then
serial_out <= bit_buf(0);
bit_buf <= bit_buf srl 1;
bit_counter := bit_counter + 1;
if(bit_counter = 10) then
internal_busy <= '0'; --finished sending
bit_counter := 0;
end if;
end if;
end if; -- ------------------------------ERROR HERE
end process transmit_bits;
end behavioural;
使用该模块的 VHDL 代码为其提供了一个波特率时钟、要发送的 8 位数据和一个表示传输应该开始的上升沿。
为了测试这一点，我将在 "tx" 引脚上连接一个逻辑分析仪，以查看串行信号的输出。我已将字节硬编码为字母 'A' (000101001)，因此我可以证明基本概念有效。
问题...
工具链 (Lattice Diamond 3.9) 无法按原样综合此设计，很明显我在对象结构上犯了错误。
这两个文件都没有语法警告或错误。除了Lattice和IEEE库提供的内置依赖，项目中没有其他VHDL文件。
运行 "Lattice Synthesis Engine" 过程的输出如下...
Analyzing Verilog file C:/lscc/diamond/3.9_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v. VERI-1482
Compile design.
Compile Design Begin
INFO - The default VHDL library search path is now "C:/Users/XXXXXXXXXXXX.XXXXXXXXXXXX/Documents/Lattice/impl1". VHDL-1504
Analyzing VHDL file c:/users/XXXXXXXXXXXX.XXXXXXXXXXXX/documents/lattice/serialtx.vhd. VHDL-1481
INFO - c:/users/XXXXXXXXXXXX.XXXXXXXXXXXX/documents/lattice/serialtx.vhd(5): analyzing entity serialtx. VHDL-1012
INFO - c:/users/XXXXXXXXXXXX.XXXXXXXXXXXX/documents/lattice/serialtx.vhd(15): analyzing architecture behavioural. VHDL-1010
unit Glue is not yet analyzed. VHDL-1485
Analyzing VHDL file c:/users/XXXXXXXXXXXX.XXXXXXXXXXXX/documents/lattice/glue.vhd. VHDL-1481
INFO - c:/users/XXXXXXXXXXXX.XXXXXXXXXXXX/documents/lattice/glue.vhd(8): analyzing entity glue. VHDL-1012
INFO - c:/users/XXXXXXXXXXXX.XXXXXXXXXXXX/documents/lattice/glue.vhd(14): analyzing architecture behavioural. VHDL-1010
unit Glue is not yet analyzed. VHDL-1485
WARNING - Net pwr has following drivers :
unit Glue is not yet analyzed. VHDL-1485
c:/users/XXXXXXXXXXXX.XXXXXXXXXXXX/documents/lattice/glue.vhd(8): executing Glue(behavioural)
WARNING - c:/users/XXXXXXXXXXXX.XXXXXXXXXXXX/documents/lattice/glue.vhd(12): replacing existing netlist Glue(behavioural). VHDL-1205
Top module name (VHDL): Glue
Last elaborated design is Glue(behavioural)
Loading NGL library 'C:/lscc/diamond/3.9_x64/ispfpga/xo2c00a/data/xo2alib.ngl'...
Loading NGL library 'C:/lscc/diamond/3.9_x64/ispfpga/xo2c00/data/xo2clib.ngl'...
Loading NGL library 'C:/lscc/diamond/3.9_x64/ispfpga/mg5g00/data/mg5glib.ngl'...
Loading NGL library 'C:/lscc/diamond/3.9_x64/ispfpga/or5g00/data/orc5glib.ngl'...
Loading device for application map from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.9_x64/ispfpga.
Package Status: Final Version 1.42.
Top-level module name = Glue.
WARNING - Initial value found on net tx will be ignored due to unrecognized driver type
WARNING - Net pwr has following drivers :
instance i2
instance internal_busy_28
ERROR - c:/users/XXXXXXXXXXXX.XXXXXXXXXXXX/documents/lattice/serialtx.vhd(45): net pwr is constantly driven from multiple places at instance internal_busy_28, on port q. VDB-1000
Done: error code 2
"net pwr is constantly driven from multiple places" 第 45 行（由代码清单中的注释 "ERROR HERE" 指示）。
我不明白这里出了什么问题，在我没有经验的眼里，internal_busy 信号看起来很低，直到它在上升沿后被驱动为高电平在 transmit_now.
我做错了什么？
错误消息不是很有帮助，但查看您的 SerialTx.vhd 文件，您已经从两个不同的进程驱动了信号 internal_busy。信号只能在一个过程中驱动，以使设计符合综合要求。
我看到的另一个错误是：tx : out std_logic := '1' --idle high。这并不像您认为的那样。您可以在其驱动程序所在的位置为信号设置初始值，但在层次结构中的其他点设置这样的值不会执行任何操作。如果您需要信号在特定状态下空闲，则必须编写代码，使信号在空闲时处于该状态。
也最好将baud_clk'event and (baud_clk = '1')等时钟检测条件换成rising_edge(baud_clk)。
我正在尝试学习 VHDL，作为练习，我正在尝试构建一个使用 RS-232 样式信号（8N1 格式）的非常简单的串行端口。
这是小项目中两个 vhdl 文件的代码...
"glue.vhd"...（顶级模块）
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use ieee.std_logic_unsigned.all;
library MACHXO2;
use MACHXO2.components.all;
entity Glue is
port(
tx : out std_logic := '1' --idle high
);
end entity Glue;
architecture behavioural of Glue is
SIGNAL clk : STD_LOGIC;
signal divider : std_logic_vector(23 downto 0);
--internal oscillator
COMPONENT OSCH
GENERIC(
NOM_FREQ: string
);
PORT(
STDBY : IN STD_LOGIC;
OSC : OUT STD_LOGIC;
SEDSTDBY : OUT STD_LOGIC);
END COMPONENT;
begin
--internal oscillator
OSCInst0: OSCH
GENERIC MAP (NOM_FREQ => "3.69")
PORT MAP (STDBY => '0', OSC => clk, SEDSTDBY => OPEN);
ser : entity SerialTX
port map (baud_clk => divider(5),
byte_to_transmit => "00101001",
transmit_now => divider(16),
busy => OPEN,
serial_out => tx);
clocker : process (clk)
begin
IF(clk'event and clk='1') then
divider <= divider + 1;
END IF;
end process clocker;
end architecture behavioural;
SerialTX.vhd...（由 glue.vhd 调用）
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity SerialTX is
port (
baud_clk : in std_logic;
byte_to_transmit : in std_ulogic_vector(7 downto 0); --the byte that we want to transmit
transmit_now : in std_logic; --a rising edge causes the byte to be sent out
busy : out std_logic; --wait for this to go low before transmiting more data
serial_out : out std_logic --the RS232 serial signal
);
end SerialTX;
architecture behavioural of SerialTX is
signal bit_buf : unsigned(9 downto 0); --(STOP bit) & (8 data bits) & (START bit)
signal internal_busy : std_logic := '0';
begin
busy <= internal_busy;
initialise_transmit : process(transmit_now, internal_busy) is
begin
if(transmit_now'event and (transmit_now = '1')) then
if((internal_busy = '0')) then
internal_busy <= '1'; --causes the "transmit_bits" process below to begin shifting out bits
bit_buf <= unsigned('1' & byte_to_transmit & '0'); --latch in the byte to our internal copy
end if;
end if;
end process initialise_transmit;
transmit_bits : process(internal_busy, baud_clk) is
variable bit_counter : integer range 0 to 10 := 0;
begin
if(baud_clk'event and (baud_clk = '1')) then
if(internal_busy = '1') then
serial_out <= bit_buf(0);
bit_buf <= bit_buf srl 1;
bit_counter := bit_counter + 1;
if(bit_counter = 10) then
internal_busy <= '0'; --finished sending
bit_counter := 0;
end if;
end if;
end if; -- ------------------------------ERROR HERE
end process transmit_bits;
end behavioural;
使用该模块的 VHDL 代码为其提供了一个波特率时钟、要发送的 8 位数据和一个表示传输应该开始的上升沿。
为了测试这一点，我将在 "tx" 引脚上连接一个逻辑分析仪，以查看串行信号的输出。我已将字节硬编码为字母 'A' (000101001)，因此我可以证明基本概念有效。
问题... 工具链 (Lattice Diamond 3.9) 无法按原样综合此设计，很明显我在对象结构上犯了错误。
这两个文件都没有语法警告或错误。除了Lattice和IEEE库提供的内置依赖，项目中没有其他VHDL文件。
运行 "Lattice Synthesis Engine" 过程的输出如下...
Analyzing Verilog file C:/lscc/diamond/3.9_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v. VERI-1482
Compile design.
Compile Design Begin
INFO - The default VHDL library search path is now "C:/Users/XXXXXXXXXXXX.XXXXXXXXXXXX/Documents/Lattice/impl1". VHDL-1504
Analyzing VHDL file c:/users/XXXXXXXXXXXX.XXXXXXXXXXXX/documents/lattice/serialtx.vhd. VHDL-1481
INFO - c:/users/XXXXXXXXXXXX.XXXXXXXXXXXX/documents/lattice/serialtx.vhd(5): analyzing entity serialtx. VHDL-1012
INFO - c:/users/XXXXXXXXXXXX.XXXXXXXXXXXX/documents/lattice/serialtx.vhd(15): analyzing architecture behavioural. VHDL-1010
unit Glue is not yet analyzed. VHDL-1485
Analyzing VHDL file c:/users/XXXXXXXXXXXX.XXXXXXXXXXXX/documents/lattice/glue.vhd. VHDL-1481
INFO - c:/users/XXXXXXXXXXXX.XXXXXXXXXXXX/documents/lattice/glue.vhd(8): analyzing entity glue. VHDL-1012
INFO - c:/users/XXXXXXXXXXXX.XXXXXXXXXXXX/documents/lattice/glue.vhd(14): analyzing architecture behavioural. VHDL-1010
unit Glue is not yet analyzed. VHDL-1485
WARNING - Net pwr has following drivers :
unit Glue is not yet analyzed. VHDL-1485
c:/users/XXXXXXXXXXXX.XXXXXXXXXXXX/documents/lattice/glue.vhd(8): executing Glue(behavioural)
WARNING - c:/users/XXXXXXXXXXXX.XXXXXXXXXXXX/documents/lattice/glue.vhd(12): replacing existing netlist Glue(behavioural). VHDL-1205
Top module name (VHDL): Glue
Last elaborated design is Glue(behavioural)
Loading NGL library 'C:/lscc/diamond/3.9_x64/ispfpga/xo2c00a/data/xo2alib.ngl'...
Loading NGL library 'C:/lscc/diamond/3.9_x64/ispfpga/xo2c00/data/xo2clib.ngl'...
Loading NGL library 'C:/lscc/diamond/3.9_x64/ispfpga/mg5g00/data/mg5glib.ngl'...
Loading NGL library 'C:/lscc/diamond/3.9_x64/ispfpga/or5g00/data/orc5glib.ngl'...
Loading device for application map from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.9_x64/ispfpga.
Package Status: Final Version 1.42.
Top-level module name = Glue.
WARNING - Initial value found on net tx will be ignored due to unrecognized driver type
WARNING - Net pwr has following drivers :
instance i2
instance internal_busy_28
ERROR - c:/users/XXXXXXXXXXXX.XXXXXXXXXXXX/documents/lattice/serialtx.vhd(45): net pwr is constantly driven from multiple places at instance internal_busy_28, on port q. VDB-1000
Done: error code 2
"net pwr is constantly driven from multiple places" 第 45 行（由代码清单中的注释 "ERROR HERE" 指示）。
我不明白这里出了什么问题，在我没有经验的眼里，internal_busy 信号看起来很低，直到它在上升沿后被驱动为高电平在 transmit_now.
我做错了什么？
错误消息不是很有帮助，但查看您的 SerialTx.vhd 文件，您已经从两个不同的进程驱动了信号 internal_busy。信号只能在一个过程中驱动，以使设计符合综合要求。
我看到的另一个错误是：tx : out std_logic := '1' --idle high。这并不像您认为的那样。您可以在其驱动程序所在的位置为信号设置初始值，但在层次结构中的其他点设置这样的值不会执行任何操作。如果您需要信号在特定状态下空闲，则必须编写代码，使信号在空闲时处于该状态。
也最好将baud_clk'event and (baud_clk = '1')等时钟检测条件换成rising_edge(baud_clk)。