modelsim verilog vsim-3365 端口太多

Question

    // Dataflow description of a 4-bit comparator  
    module FourBcompare ( 
      output        A_lt_B, A_eq_B, A_gt_B, 
      input [3: 0]  A, B
    );
      assign A_lt_B = (A < B);
      assign A_gt_B = (A > B);
      assign A_eq_B = (A == B);
    endmodule

//'timescale 1 ps / 1 ps
module t_fourBcompare;

  reg   [7: 0]AB;
  wire  t_A_lt_B;
  wire  t_A_eq_B;
  wire  t_A_gt_B;
  parameter stop_time = 100;

  FourBcompare M1 (   t_A_lt_B, t_A_eq_B, t_A_gt_B ,
              AB[7],AB[6],AB[5],AB[4],
              AB[3],AB[2],AB[1],AB[0]
           );

  initial # stop_time $finish;
  initial begin                 // Stimulus generator
        AB = 8'b00000000;
    repeat (256)
   #10 AB = AB +1'b1;
  end

可以编译，但是不能在modelsim上模拟

错误信息如下：

# Compile of FourBcompare.v was successful.
# Compile of t_fourBcompare.v was successful.
# 2 compiles, 0 failed with no errors.
vsim work.t_fourBcompare
# vsim work.t_fourBcompare 
# Start time: 01:43:58 on May 02,2017
# Loading work.t_fourBcompare
# Loading work.FourBcompare
# ** Fatal: (vsim-3365) D:/util/t_fourBcompare.v(10): Too many port connections. Expected 5, found 11.
#    Time: 0 ps  Iteration: 0  Instance: /t_fourBcompare/M1 File: D:/util/FourBcompare.v
# FATAL ERROR while loading design
# Error loading design
# End time: 01:43:58 on May 02,2017, Elapsed time: 0:00:00
# Errors: 1, Warnings: 0

Answer 1

该消息表示 FourBcompare 模块有 5 个信号（2 个输入 + 3 个输出），但您正尝试将 11 个信号连接到它。端口 input [3:0] A 算作一个信号，而不是 4 个。

这是消除错误的一种方法，但您必须确定它是否符合您的情况的正确逻辑：

  FourBcompare M1 (   t_A_lt_B, t_A_eq_B, t_A_gt_B ,
              {AB[7],AB[6],AB[5],AB[4]},
              {AB[3],AB[2],AB[1],AB[0]}
           );

我使用连接运算符 {} 将各个位组合到总线中。请参阅免费的 IEEE Std 1800-2012，第 11.4.12 串联运算符 部分。现在，一个 4 位值 {AB[7],AB[6],AB[5],AB[4]} 连接到 4 位 A 信号。

注：{AB[7],AB[6],AB[5],AB[4]}可以简化为AB[7:4]。

modelsim verilog vsim-3365 端口太多

modelsim verilog vsim-3365 too many port

verilog

modelsim

digital