VHDL 中的 5 秒定时器

Question

我在 fpga 中使用 50MHz 时钟并尝试制作 5 秒定时器。 cnt_t 以下达到 5 x 50MHz (x"0EE6B280" --> 250,000,000) 然后使 time_tick_32 变为 1 并使 cnt_t <= x"00000000";。下面的代码不起作用永远不会 time_tick_32 得到 1.

signal cnt_t    : STD_LOGIC_VECTOR(31 DOWNTO 0) := x"00000000";
signal time_tick : STD_LOGIC:= '0' ;
signal time_tick_32 : STD_LOGIC_VECTOR(31 DOWNTO 0):= x"00000000";


process (clk_50) IS
    begin
      if falling_edge(clk_50)  then
      cnt_t <= cnt_t + '1';
      end if;
    if (cnt_t = x"0EE6B280") then --if 5 seconds  
        time_tick <= '1';
        cnt_t <= x"00000000";
        time_tick_32(0)<=time_tick;
    else
        time_tick <= '0';
        time_tick_32(0)<=time_tick;
    end if;

end process;

Answer 1

尝试：

signal cnt_t    : STD_LOGIC_VECTOR(31 DOWNTO 0) := x"00000000";
signal time_tick : STD_LOGIC:= '0' ;
signal time_tick_32 : STD_LOGIC_VECTOR(31 DOWNTO 0):= x"00000000";


-- I assume you begin your architecture somewhere
-- Can make the following a concurrent statement
-- (unless it is some kind of shift reg assigned in a diff process...
-- then you will get multiple driver issues)
time_tick_32(0) <= time_tick;

process (clk_50) IS
begin
    if rising_edge(clk_50)  then -- Changed to rising_edge; 
                                -- Any particular reason you are using falling_edge?
        if (cnt_t = x"0EE6B280") then --if 5 seconds  
            time_tick <= '1';
            cnt_t <= x"00000000";
        else
            time_tick <= '0';
            cnt_t <= cnt_t + '1';  
        end if;
    end if;
end process;

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