VHDL：使用 "With Select When" 语句时出错

Question

我正在使用 Altera Max V 和 Quartus 学习 VHDL 来做一些示例，但在使用 "With Select when" 语句时遇到了麻烦。我有一个简单的 2-4 解码器如下：

library ieee;
use ieee.std_logic_1164.all;

entity lesson9 is
    port(
        x: in std_logic_vector(1 downto 0);
        en: in std_logic;
        y: out std_logic_vector(3 downto 0)
    );
end lesson9;

architecture rtl of lesson9 is

signal outputBuff: std_logic_vector(3 downto 0);

begin
    decoder2to4: process(x)
    begin
        with x select
            outputBuff <= "0001" when "00",
                          "0010" when "01",
                          "0100" when "10",
                          "1000" when "11";
    end process decoder2to4;

    y <= outputBuff;
end rtl;

我收到错误消息：

near text "with"; expecting "end", or "(", or an identifer ("with" is a reserved keyword), pr a sequential statement

我尝试检查我的代码但找不到问题？

Answer 1

with ... select语句是在进程外使用的并发信号赋值语句：

architecture rtl of lesson9 is

signal outputBuff: std_logic_vector(3 downto 0);

begin
    with x select
        outputBuff <= "0001" when "00",
                      "0010" when "01",
                      "0100" when "10",
                      "1000" when "11";

    y <= outputBuff when en='1' else (others=>'0');
end rtl;

我还在输出赋值语句中添加了en信号。

注意：我没有模拟那个代码片段。

VHDL：使用 "With Select When" 语句时出错

VHDL: error when using "With Select When" Statement

vhdl

quartus