VHDL Code Error: "Error (10818): Can't infer register for <name> at <location> because it does not hold its value outside the clock edge"

Question

我知道这个错误已经在SO上遇到过好几次了，但是作为一个初学者我仍然看不出如何在我自己的代码中解决这个错误。错误和代码都打印在下面，感谢任何人的输入。

Error (10818): Can't infer register for count[0] at 5bit_PHreg_vhdl.vhd(21) because it does not hold its value outside the clock edge

'count' 的每一位都会重复错误，并参考代码中注明的行。

ARCHITECTURE behavioral OF 5bit_PHreg_vhdl IS
SIGNAL count    :   STD_LOGIC_VECTOR(4 DOWNTO 0);

BEGIN
    PROCESS(reset, clk, SHR_EN)
        BEGIN
-- Check if asynchronous reset is 0
        IF reset = '0' THEN --ERROR OCCURS HERE
                count <= "00000";
-- Check if rising edge
        ELSIF (clk'EVENT AND clk = '1') THEN
                IF LD_EN = '1' THEN
                    count <= FA_in;
                END IF;
-- Check if SHR_EN is active
        ELSIF (SHR_EN = '1') THEN
                count(4) <= c_in;
                count(3) <= count(4);
                count(2) <= count(3);
                count(1) <= count(2);
                count(0) <= count(1);
                c_out <= count(0);
        END IF;
    END PROCESS;
    PH_reg_out <= count;
END behavioral;

Answer 1

ELSIF (SHR_EN = '1') THEN 在复位和时钟边沿条件之外，它的形式不能被合成识别。

如果已注册，请将其和以下分配移至前端。从进程敏感度列表中删除 SHR_EN。

同样在 VHDL 中，名称不能以数字开头，5bit_PHreg_vhdl 作为实体名称是无效的。

修复这些并填写缺失的实体声明：

library ieee;
use ieee.std_logic_1164.all;

entity PH_reg_5_bit is
    port (
        reset:      in  std_logic;
        clk:        in  std_logic;
        LD_EN:      in  std_logic;
        SHR_EN:     in  std_logic;
        FA_in:      in  std_logic_vector (4 downto 0);
        c_in:       in  std_logic;
        c_out:      out std_logic;
        PH_reg_out: out std_logic_vector (4 downto 0)
    );
end entity;

ARCHITECTURE behavioral OF PH_reg_5_bit IS
    SIGNAL count    :   STD_LOGIC_VECTOR(4 DOWNTO 0);

BEGIN
    PROCESS (reset, clk) -- , SHR_EN)
        BEGIN
-- Check if asynchronous reset is 0
        IF reset = '0' THEN --ERROR OCCURS HERE
                count <= "00000";
-- Check if rising edge
        ELSIF (clk'EVENT AND clk = '1') THEN
                IF LD_EN = '1' THEN
                    count <= FA_in;
        -- Check if SHR_EN is active
                ELSIF (SHR_EN = '1') THEN
                        count(4) <= c_in;
                        count(3) <= count(4);
                        count(2) <= count(3);
                        count(1) <= count(2);
                        count(0) <= count(1);
                END IF;
-- -- Check if SHR_EN is active
--         ELSIF (SHR_EN = '1') THEN
--                 count(4) <= c_in;
--                 count(3) <= count(4);
--                 count(2) <= count(3);
--                 count(1) <= count(2);
--                 count(0) <= count(1);
--                 c_out <= count(0);
        END IF;
    END PROCESS;

    c_out <= count(0);  -- c_out not separately registered
    PH_reg_out <= count;
END behavioral;

您的代码分析成功。

实体名称很好地表明您还没有模拟您的设计。

注意条件顺序意味着加载优先于移动。

我怀疑不应该注册 c_out 允许使用 c_in 和 c_out 将移位寄存器实例连接成更大的移位寄存器。这意味着它的赋值应该在包含时钟边沿事件的 if 语句之外，它可以紧挨着另一个输出引脚赋值。

VHDL Code Error: "Error (10818): Can't infer register for <name> at <location> because it does not hold its value outside the clock edge"

VHDL Code Error: "Error (10818): Can't infer register for <name> at <location> because it does not hold its value outside the clock edge"

vhdl

digital

quartus