Vhdl-Code testbench 为什么没有声明端口
Vhdl-Code testbench why are there no ports declared
为什么 VHDL 代码测试台中没有声明端口？
测试平台是一个封闭的系统。被测设计 (DUT) 的所有输入均由测试平台驱动。测试台可以观察到被测设计的所有输出。因此，测试台没有输入或输出。
VHDL 标准中未定义 Testbench，因此需要向其他权威机构提出上诉。
参见 电子设计自动化手册，Dirk Jansen 编着，2003 年，第 137 页：
4.10 Test Bench
The test of proper functionality of a VHDL model ideally starts during its development. To begin with, input signals like clock and data to stimulate the circuit and to produce response at the outputs are of interest. Later in the development cycle signal behavior at the output is of primary interest.
To set up a simulation environment a so called test bench, VHDL is highly suitable. The capabilities of VHDL can be used without any restrictions. From an external point of view the test bench is a closed box surrounding the object under test thus producing an autonomous system. The test bench should be a good and complete description of the environment the circuit is exposed to.
The most important characteristic of a test bench is an empty port list stated in a VHDL description one level of hierarchy above. Here the description under test is instantiated as a component. The purpose of a test bench is to produce suitable input signals and to check the outputs in a way that a time consuming visual control is not necessary. There are three parts which determine the structure of a test bench:
• A stimuli model or the definition of test vectors at the inputs;
• The VHDL description under test (device under test, DUT);
• A response model to check or store the results of the simulation.
所以它是一个仿真模型，包含被测设备（您的可实施设计模型）、输入激励，并且还可能提供预期结果和验证它们的方法。
参见 IEEE 标准 1076-2008 14.2 设计层次结构的阐述，第 7 段：
An implementation may allow, but is not required to allow, a design entity at the root of a design hierarchy to have generics and ports. ... ".
不需要 VHDL 实现来详细说明和模拟具有顶级接口列表的模型。如果您的模型的顶层没有任何泛型端口，那么您就安全了。如果泛型是允许存在的端口，它们不会做任何有趣的事情。
基于激励-信号事件发生的VHDL模型仿真。一旦没有更多的信号事件，预定的模拟时间将提前到 Time'HIGH，模拟将结束。
具有未连接端口的顶级模型将简单地执行初始化并且完全没有测试台，除非模型包含张弛振荡器调用延迟 - 并且无法合成。
我们在测试台中提供以 VHDL 编写的算法激励模型，以在为验证目的而行使功能的同时保持模拟活跃。
为什么 VHDL 代码测试台中没有声明端口？
测试平台是一个封闭的系统。被测设计 (DUT) 的所有输入均由测试平台驱动。测试台可以观察到被测设计的所有输出。因此，测试台没有输入或输出。
VHDL 标准中未定义 Testbench，因此需要向其他权威机构提出上诉。
参见 电子设计自动化手册，Dirk Jansen 编着，2003 年，第 137 页：
4.10 Test Bench
The test of proper functionality of a VHDL model ideally starts during its development. To begin with, input signals like clock and data to stimulate the circuit and to produce response at the outputs are of interest. Later in the development cycle signal behavior at the output is of primary interest.
To set up a simulation environment a so called test bench, VHDL is highly suitable. The capabilities of VHDL can be used without any restrictions. From an external point of view the test bench is a closed box surrounding the object under test thus producing an autonomous system. The test bench should be a good and complete description of the environment the circuit is exposed to.
The most important characteristic of a test bench is an empty port list stated in a VHDL description one level of hierarchy above. Here the description under test is instantiated as a component. The purpose of a test bench is to produce suitable input signals and to check the outputs in a way that a time consuming visual control is not necessary. There are three parts which determine the structure of a test bench:
• A stimuli model or the definition of test vectors at the inputs;
• The VHDL description under test (device under test, DUT);
• A response model to check or store the results of the simulation.
所以它是一个仿真模型，包含被测设备（您的可实施设计模型）、输入激励，并且还可能提供预期结果和验证它们的方法。
参见 IEEE 标准 1076-2008 14.2 设计层次结构的阐述，第 7 段：
An implementation may allow, but is not required to allow, a design entity at the root of a design hierarchy to have generics and ports. ... ".
不需要 VHDL 实现来详细说明和模拟具有顶级接口列表的模型。如果您的模型的顶层没有任何泛型端口，那么您就安全了。如果泛型是允许存在的端口，它们不会做任何有趣的事情。
基于激励-信号事件发生的VHDL模型仿真。一旦没有更多的信号事件，预定的模拟时间将提前到 Time'HIGH，模拟将结束。
具有未连接端口的顶级模型将简单地执行初始化并且完全没有测试台，除非模型包含张弛振荡器调用延迟 - 并且无法合成。
我们在测试台中提供以 VHDL 编写的算法激励模型，以在为验证目的而行使功能的同时保持模拟活跃。