使用 Xilinx Logicore Boxes 时出现测试平台错误
Testbench errors when using Xilinx Logicore Boxes
我正在制作一个带有用户输入的过滤器组，现在我正在尝试测试当前的设计，看看是否需要修复任何东西。目前，我可以生成比特流并查看我的 LED 的变化。然而，在测试台中，LED 波形不会从其初始零状态移动。另外，我的过滤器似乎根本不起作用。
我用LogiCore做了一个FIR，用DDS编译器做了一个正弦波来激励它。我正在使用 DSP48 对输出信号进行调幅。
我有两个我认为需要的 ISim 库。我不太清楚为什么我的输出没有被分配？
我看过文档，我使用的是 Xilinx 的 ISIM，所以我不需要重新编译模拟库，我相信......我的想法是不是错了？
在我的模拟中间有一个地方存在我的数据，但我不知道它是否有效。
欢迎提供任何帮助。
我的顶级模块。
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:56:05 03/25/2015
-- Design Name:
-- Module Name: Filter_Box - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Filter_Box is
Port ( Board_Clock : in STD_LOGIC;
--Filter_Clock : in STD_LOGIC;
--Input_Sample : in STD_LOGIC_VECTOR (15 downto 0);
--Out_data : out STD_LOGIC_VECTOR (15 downto 0);
led : out STD_LOGIC_VECTOR (3 downto 0);
Mixer_Controls : in STD_LOGIC_VECTOR (1 downto 0));
end Filter_Box;
architecture Behavioral of Filter_Box is
--
-- Component statements here, these should all be filters and/or DSP cores
-- unless otherwise noted.
--uses 1 dsp core and 1 bram
component Low_Pass
port (
clk : in std_logic; --core clock
rfd : out std_logic; --filter ready for data flag
rdy : out std_logic; --filter output ready flag
din : in std_logic_vector(15 downto 0); --data in (To be filterd)
dout : out std_logic_vector(15 downto 0)); --data out (has been filtered)
end component;
-- Uses 1 dsp core (3 dsp registers)
COMPONENT Mixer_controls_DSP_slice
PORT (
clk : IN STD_LOGIC;
a : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
b : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
p : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END COMPONENT;
-- This sine wave box is for testing purposes only
COMPONENT Sine_Wave
PORT (
clk : IN STD_LOGIC;
pinc_in : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
sine : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END COMPONENT;
--
-- Singal instantiations
--
signal rfd : std_logic;
signal rdy : std_logic;
signal din : std_logic_vector (15 downto 0) := X"0000";
signal dout : std_logic_vector (15 downto 0) := X"0000";
signal Low_Pass_Final_Data_Signal : std_logic_vector (15 downto 0) := X"0000";
signal pinc_in : std_logic_vector (15 downto 0) := X"0001";
begin
--
--This register will controll all the singals
-- in the module and should direct the acctual
-- signals to their formal signals
Internal_Signal_Traffic_Controller :
process (Board_Clock) is
variable count : std_logic_vector (31 downto 0) := (others => '0');
begin
if rising_edge(Board_Clock) then
led <= count(31) & count (30) & count(29) & count(28);
count := count +1;
end if;
end process;
--low pass filter instance, must use the filter clock,
-- currently filter clock is set to 500 MHZ
-- This will be the DSP clock as well
Low_Pass_Filter_Instance_Number_One :
Low_Pass port map (
clk => Board_Clock,
rfd => rfd,
rdy => rdy,
din => din,
dout => dout);
-- Mixer instance to multiply filter outputs
-- by fifo controll inputs, the output
-- should then be passed to the adder core
-- to reassemble the signal and put it out
-- to whichever port is needed
Filter_Instance_One_Amplitude_Controller :
Mixer_controls_DSP_slice PORT MAP (
clk => Board_Clock,
a => Mixer_Controls,
b => dout,
p => Low_Pass_Final_Data_Signal
);
-- This is the sinewave testing box
-- it should be deleted or commented
-- out after testing has been done
Sine_Wave_Testing_Box : Sine_Wave
PORT MAP (
clk => Board_Clock,
pinc_in => pinc_in,
sine => din
);
--Out_data <= Low_Pass_Final_Data_Signal;
end Behavioral;
我的测试台
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:00:04 03/25/2015
-- Design Name:
-- Module Name: D:/Dropbox/ECE.CLASSES/SeniorD/Filter_Top_Module/Filter_Box/Test_Bench_of_Filter_Module.vhd
-- Project Name: Filter_Box
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: Filter_Box
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.VComponents.all;
library UNIMACRO;
use UNIMACRO.Vcomponents.all;
ENTITY Test_Bench_of_Filter_Module IS
END Test_Bench_of_Filter_Module;
ARCHITECTURE behavior OF Test_Bench_of_Filter_Module IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT Filter_Box
PORT(
Board_Clock : IN std_logic;
--Out_data : OUT std_logic;
led : OUT std_logic_vector(3 downto 0);
Mixer_Controls : IN std_logic_vector(1 downto 0)
);
END COMPONENT;
--Inputs
signal Board_Clock : std_logic := '0';
signal Mixer_Controls : std_logic_vector(1 downto 0) := (others => '1');
--Outputs
signal Out_data : std_logic;
signal led : std_logic_vector(3 downto 0);
-- Clock period definitions
constant Board_Clock_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: Filter_Box PORT MAP (
Board_Clock => Board_Clock,
--Out_data => Out_data,
led => led,
Mixer_Controls => Mixer_Controls
);
-- Clock process definitions
Board_Clock_process :process
begin
Board_Clock <= '0';
wait for Board_Clock_period/2;
Board_Clock <= '1';
wait for Board_Clock_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for Board_Clock_period*10;
-- insert stimulus here
wait;
end process;
END;
这是我得到的波形示例，我好奇的数据在哪里还活着，但后来又变回 X。
编辑：这些 DSP 内核设计为以 500MHz 驱动，滤波器的采样频率为 100KHz，低通截止频率为 400Hz。
Xilinx 的 FIR 内核不接受每个时钟生成 1 个样本，而是每 N 个时钟周期生成 1 个样本，其中 N 取决于滤波器的参数，尤其是其长度和架构。
我建议你看看FIR编译器数据表，并开始监视信号rfd（准备好数据，指示何时读取输入）和 rdy（准备好，表示什么时候输出有效）。
我正在制作一个带有用户输入的过滤器组，现在我正在尝试测试当前的设计，看看是否需要修复任何东西。目前，我可以生成比特流并查看我的 LED 的变化。然而，在测试台中，LED 波形不会从其初始零状态移动。另外，我的过滤器似乎根本不起作用。
我用LogiCore做了一个FIR，用DDS编译器做了一个正弦波来激励它。我正在使用 DSP48 对输出信号进行调幅。
我有两个我认为需要的 ISim 库。我不太清楚为什么我的输出没有被分配？
我看过文档，我使用的是 Xilinx 的 ISIM，所以我不需要重新编译模拟库，我相信......我的想法是不是错了？
在我的模拟中间有一个地方存在我的数据，但我不知道它是否有效。
欢迎提供任何帮助。
我的顶级模块。
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:56:05 03/25/2015
-- Design Name:
-- Module Name: Filter_Box - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Filter_Box is
Port ( Board_Clock : in STD_LOGIC;
--Filter_Clock : in STD_LOGIC;
--Input_Sample : in STD_LOGIC_VECTOR (15 downto 0);
--Out_data : out STD_LOGIC_VECTOR (15 downto 0);
led : out STD_LOGIC_VECTOR (3 downto 0);
Mixer_Controls : in STD_LOGIC_VECTOR (1 downto 0));
end Filter_Box;
architecture Behavioral of Filter_Box is
--
-- Component statements here, these should all be filters and/or DSP cores
-- unless otherwise noted.
--uses 1 dsp core and 1 bram
component Low_Pass
port (
clk : in std_logic; --core clock
rfd : out std_logic; --filter ready for data flag
rdy : out std_logic; --filter output ready flag
din : in std_logic_vector(15 downto 0); --data in (To be filterd)
dout : out std_logic_vector(15 downto 0)); --data out (has been filtered)
end component;
-- Uses 1 dsp core (3 dsp registers)
COMPONENT Mixer_controls_DSP_slice
PORT (
clk : IN STD_LOGIC;
a : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
b : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
p : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END COMPONENT;
-- This sine wave box is for testing purposes only
COMPONENT Sine_Wave
PORT (
clk : IN STD_LOGIC;
pinc_in : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
sine : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END COMPONENT;
--
-- Singal instantiations
--
signal rfd : std_logic;
signal rdy : std_logic;
signal din : std_logic_vector (15 downto 0) := X"0000";
signal dout : std_logic_vector (15 downto 0) := X"0000";
signal Low_Pass_Final_Data_Signal : std_logic_vector (15 downto 0) := X"0000";
signal pinc_in : std_logic_vector (15 downto 0) := X"0001";
begin
--
--This register will controll all the singals
-- in the module and should direct the acctual
-- signals to their formal signals
Internal_Signal_Traffic_Controller :
process (Board_Clock) is
variable count : std_logic_vector (31 downto 0) := (others => '0');
begin
if rising_edge(Board_Clock) then
led <= count(31) & count (30) & count(29) & count(28);
count := count +1;
end if;
end process;
--low pass filter instance, must use the filter clock,
-- currently filter clock is set to 500 MHZ
-- This will be the DSP clock as well
Low_Pass_Filter_Instance_Number_One :
Low_Pass port map (
clk => Board_Clock,
rfd => rfd,
rdy => rdy,
din => din,
dout => dout);
-- Mixer instance to multiply filter outputs
-- by fifo controll inputs, the output
-- should then be passed to the adder core
-- to reassemble the signal and put it out
-- to whichever port is needed
Filter_Instance_One_Amplitude_Controller :
Mixer_controls_DSP_slice PORT MAP (
clk => Board_Clock,
a => Mixer_Controls,
b => dout,
p => Low_Pass_Final_Data_Signal
);
-- This is the sinewave testing box
-- it should be deleted or commented
-- out after testing has been done
Sine_Wave_Testing_Box : Sine_Wave
PORT MAP (
clk => Board_Clock,
pinc_in => pinc_in,
sine => din
);
--Out_data <= Low_Pass_Final_Data_Signal;
end Behavioral;
我的测试台
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:00:04 03/25/2015
-- Design Name:
-- Module Name: D:/Dropbox/ECE.CLASSES/SeniorD/Filter_Top_Module/Filter_Box/Test_Bench_of_Filter_Module.vhd
-- Project Name: Filter_Box
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: Filter_Box
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.VComponents.all;
library UNIMACRO;
use UNIMACRO.Vcomponents.all;
ENTITY Test_Bench_of_Filter_Module IS
END Test_Bench_of_Filter_Module;
ARCHITECTURE behavior OF Test_Bench_of_Filter_Module IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT Filter_Box
PORT(
Board_Clock : IN std_logic;
--Out_data : OUT std_logic;
led : OUT std_logic_vector(3 downto 0);
Mixer_Controls : IN std_logic_vector(1 downto 0)
);
END COMPONENT;
--Inputs
signal Board_Clock : std_logic := '0';
signal Mixer_Controls : std_logic_vector(1 downto 0) := (others => '1');
--Outputs
signal Out_data : std_logic;
signal led : std_logic_vector(3 downto 0);
-- Clock period definitions
constant Board_Clock_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: Filter_Box PORT MAP (
Board_Clock => Board_Clock,
--Out_data => Out_data,
led => led,
Mixer_Controls => Mixer_Controls
);
-- Clock process definitions
Board_Clock_process :process
begin
Board_Clock <= '0';
wait for Board_Clock_period/2;
Board_Clock <= '1';
wait for Board_Clock_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for Board_Clock_period*10;
-- insert stimulus here
wait;
end process;
END;
这是我得到的波形示例，我好奇的数据在哪里还活着，但后来又变回 X。
编辑：这些 DSP 内核设计为以 500MHz 驱动，滤波器的采样频率为 100KHz，低通截止频率为 400Hz。
Xilinx 的 FIR 内核不接受每个时钟生成 1 个样本，而是每 N 个时钟周期生成 1 个样本，其中 N 取决于滤波器的参数，尤其是其长度和架构。
我建议你看看FIR编译器数据表，并开始监视信号rfd（准备好数据，指示何时读取输入）和 rdy（准备好，表示什么时候输出有效）。