如何使用 16 位 LFSR 创建伪随机序列

Question

我正在尝试生成一个 16 位的随机序列。问题是输出处于未定义状态。我觉得这是由于那些异或语句中的并行处理。所以我已经推迟了，但它仍然不起作用。

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity random_data_generator is
  port (
    por             :   in  STD_LOGIC;
    sys_clk         :   in  STD_LOGIC;
    random_flag     :   in  STD_LOGIC;
    random_data     :   out STD_LOGIC_vector (15 downto 0)
  );
end random_data_generator;

architecture Behavioral of random_data_generator is
  signal q          :   std_logic_vector(15 downto 0);
  signal n1,n2,n3   :   std_logic;


begin
  process(sys_clk)
  begin
  if(por='0') then 
    q<= "1001101001101010";
    elsif(falling_edge(sys_clk)) then
        if(random_flag='1') then
        n1<= q(15) xor q(13);
        n2<= n1 xor q(11) after 10 ns;
        n3<= n2 xor q(10) after 10 ns;
        q<= q(14 downto 0) & n3 after 10 ns;
    end if;
    end if;
  end process;
  random_data <= q;
end Behavioral;

Answer 1

对 LFSR 进行一些小的结构更改：

library ieee;
use ieee.std_logic_1164.all;

entity random_data_generator is
    port (
        por:                in  std_logic;
        sys_clk:            in  std_logic;
        random_flag:        in  std_logic;
        random_data:        out std_logic_vector (15 downto 0)
    );
end entity random_data_generator;

architecture behavioral of random_data_generator is
    signal q:             std_logic_vector(15 downto 0);
    signal n1, n2, n3:    std_logic;
begin
    process (por, sys_clk) -- ADDED por to sensitivity list
    begin
        if por = '0' then 
            q <= "1001101001101010";
        elsif falling_edge(sys_clk) then
            if random_flag = '1' then
                -- REMOVED intermediary products as flip flops
                q <= q(14 downto 0) & n3;  -- REMOVED after 10 ns;
            end if;
        end if;
    end process;
    -- MOVED intermediary products to concurrent signal assignments:
    n1 <= q(15) xor q(13);
    n2 <= n1 xor q(11); --  REMOVED after 10 ns;
    n3 <= n2 xor q(10); --  REMOVED after 10 ns;

    random_data <= q;
end architecture behavioral;

这些更改通过将这些赋值提升为并发信号赋值语句来移除 n1、n2 和 n3 触发器。产生“U”的根本问题是这些触发器没有被初始化。它们是触发器，因为它们的赋值在 if 语句内，在 sys_clk.

的下降沿带有 elsif 条件。

添加测试台：

library ieee;
use ieee.std_logic_1164.all;

entity rng_tb is
end entity;

architecture foo of rng_tb is
    signal por:         std_logic;
    signal sys_clk:     std_logic := '0';
    signal random_flag: std_logic;
    signal random_data: std_logic_vector (15 downto 0);
begin
DUT:
    entity work.random_data_generator
        port map (
            por => por,
            sys_clk => sys_clk,
            random_flag => random_flag,
            random_data => random_data
        );
CLOCK:
    process
    begin
        wait for 5 ns;
        sys_clk <= not sys_clk;
        if now > 2800 ns then
            wait;
        end if;
    end process;
STIMULI:
    process
    begin
        por <= '1';
        random_flag <= '0';
        wait until falling_edge(sys_clk);
        por <= '0';
        wait until falling_edge(sys_clk);
        wait for 1 ns;
        por <= '1';
        wait until falling_edge(sys_clk);
        random_flag <= '1';
        wait;
    end process;
end architecture;

分析、详细说明和模拟测试平台给出：

使用 16 位线性反馈移位寄存器 (LFSR) 显示长度大于 16 的伪随机序列。

如何使用 16 位 LFSR 创建伪随机序列

How to create a pseudo-random sequence with a 16 bit LFSR

vhdl

xilinx-ise