如何在 VHDL 中的时钟中暂停 2Hz？
How can I do a pause of 2Hz in a clock in VHDL?
我是 VHDL 的技术新手，我需要在 VHDL 程序中为一个计数器项目暂停 2Hz 或 0.5Hz。
另一方面，我有以下代码：
architecture behavior of Counter is
signal q: std_logic_vector(7 downto 0);
begin
process(clock, choose)
begin
if clear = '1' then
q <= q - q;
else
if rising_edge(clock) then
-- when choose is '1', the process if for increment
if(choose = '1') then
case incodec is
when "001" => q <= q + 1;
when "011" => q <= q + 10;
when "111" => q <= q + 11;
when others => q <= q;
end case;
-- when choose is '0', the process if for decrement
elsif choose = '0' then
case incodec is
when "001" => q <= q - 1;
when "011" => q <= q - 10;
when "111" => q <= q - 11;
when others => q <= q;
end case;
end if;
end if;
end if;
case q(7 downto 4) is
-- 6543210
when "0000" => hex7 <= "1000000"; --0
when "0001" => hex7 <= "1111001"; --1
when "0010" => hex7 <= "0100100"; --2
when "0011" => hex7 <= "0110000"; --3
when "0100" => hex7 <= "0011001"; --4
when "0101" => hex7 <= "0010010"; --5
when "0110" => hex7 <= "0000010"; --6
when "0111" => hex7 <= "1111000"; --7
when "1000" => hex7 <= "0000000"; --8
when "1001" => hex7 <= "0010000"; --9
when "1010" => hex7 <= "0001000"; --10/A
when "1011" => hex7 <= "0000011"; --11/B/b
when "1100" => hex7 <= "1000110"; --12/C
when "1101" => hex7 <= "0100001"; --13/D/d
when "1110" => hex7 <= "0000110"; --14/E
when "1111" => hex7 <= "0001110"; --15/F
when others => hex7 <= "0111111"; -- -
end case;
case q(3 downto 0) is
-- 6543210
when "0000" => hex6 <= "1000000"; --0
when "0001" => hex6 <= "1111001"; --1
when "0010" => hex6 <= "0100100"; --2
when "0011" => hex6 <= "0110000"; --3
when "0100" => hex6 <= "0011001"; --4
when "0101" => hex6 <= "0010010"; --5
when "0110" => hex6 <= "0000010"; --6
when "0111" => hex6 <= "1111000"; --7
when "1000" => hex6 <= "0000000"; --8
when "1001" => hex6 <= "0010000"; --9
when "1010" => hex6 <= "0001000"; --10/A
when "1011" => hex6 <= "0000011"; --11/B/b
when "1100" => hex6 <= "1000110"; --12/C
when "1101" => hex6 <= "0100001"; --13/D/d
when "1110" => hex6 <= "0000110"; --14/E
when "1111" => hex6 <= "0001110"; --15/F
when others => hex6 <= "0111111"; -- -
end case;
end behavior
程序编译时出现如下错误：
Error (10818): Can't infer register for "q[0]" at Counter.vhd(28) because it does not hold its value outside the clock edge
I don't know what is means
请帮帮我:(
您的代码包含多个错误：
- 不要使用 Synopsys 包进行算术运算。
使用包 numeric_std 和类型 signed and/or unsigned 代替。
q表示状态，会合成为触发器
所以在一个FPGA技术上，初始化它们：:= (others => '0')clear是一个异步信号，所以把它列在敏感列表中。choose是同步信号，所以不要列在敏感列表中。- 当您想添加数字 1、2、3 时，请使用适当的整数文字或将您的文字明确指定为二进制。默认为十进制。
- 使用变量将通过消除重复来缩短代码。
- 清除
q 应该通过使用聚合分配所有零来完成：(others => '0').
- for 循环和另一个变量可以进一步减少您的代码并删除另一大段重复代码。
- 用户变量
hex 也将删除一个额外的寄存器级，这很可能不是大多数设计者想要的。
- 您评论了 7 段显示器的段名称
6543210，但段通常命名为 GFEDCBA。
- 您应该将 7 段解码器放入单独的实体或函数中以提高可重用性。
- 你的7段显示代码是低电平有效，但是设计者应该写出高电平有效的代码。低活性是由于电路板或显示器设计而不是解码器的责任。将
hex 赋值给 hex7. 时可以进行反转
改进代码如下：
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Counter is
-- ...
end entity;
architecture behavior of Counter is
signal q : unsigned(7 downto 0) := (others => '0');
begin
process(clock, clear)
variable decoded : positive;
variable hex : std_logic_vector(13 downto 0);
begin
case incodec is
when "001" => decoded := 1;
when "011" => decoded := 2;
when "111" => decoded := 3;
when others => decoded := 0;
end case;
if clear = '1' then
q <= (others => '0');
elsif rising_edge(clock) then
if(choose = '1') then -- when choose is '1', the process if for increment
q <= q + decoded;
elsif (choose = '0') then -- when choose is '0', the process if for decrement
q <= q - decoded;
end if;
end if;
for i in 0 to 1 loop
case q(i*4+7 downto i*4) is -- 6543210
when "0000" => hex(i*7+6 downto i*7) := "1000000"; --0
when "0001" => hex(i*7+6 downto i*7) := "1111001"; --1
when "0010" => hex(i*7+6 downto i*7) := "0100100"; --2
when "0011" => hex(i*7+6 downto i*7) := "0110000"; --3
when "0100" => hex(i*7+6 downto i*7) := "0011001"; --4
when "0101" => hex(i*7+6 downto i*7) := "0010010"; --5
when "0110" => hex(i*7+6 downto i*7) := "0000010"; --6
when "0111" => hex(i*7+6 downto i*7) := "1111000"; --7
when "1000" => hex(i*7+6 downto i*7) := "0000000"; --8
when "1001" => hex(i*7+6 downto i*7) := "0010000"; --9
when "1010" => hex(i*7+6 downto i*7) := "0001000"; --10/A
when "1011" => hex(i*7+6 downto i*7) := "0000011"; --11/b
when "1100" => hex(i*7+6 downto i*7) := "1000110"; --12/C
when "1101" => hex(i*7+6 downto i*7) := "0100001"; --13/d
when "1110" => hex(i*7+6 downto i*7) := "0000110"; --14/E
when "1111" => hex(i*7+6 downto i*7) := "0001110"; --15/F
when others => hex(i*7+6 downto i*7) := "0111111"; -- -
end case;
end loop;
hex7 <= hex(13 downto 7);
hex6 <= hex(6 downto 0);
end process;
end architecture;
我是 VHDL 的技术新手，我需要在 VHDL 程序中为一个计数器项目暂停 2Hz 或 0.5Hz。
另一方面，我有以下代码：
architecture behavior of Counter is
signal q: std_logic_vector(7 downto 0);
begin
process(clock, choose)
begin
if clear = '1' then
q <= q - q;
else
if rising_edge(clock) then
-- when choose is '1', the process if for increment
if(choose = '1') then
case incodec is
when "001" => q <= q + 1;
when "011" => q <= q + 10;
when "111" => q <= q + 11;
when others => q <= q;
end case;
-- when choose is '0', the process if for decrement
elsif choose = '0' then
case incodec is
when "001" => q <= q - 1;
when "011" => q <= q - 10;
when "111" => q <= q - 11;
when others => q <= q;
end case;
end if;
end if;
end if;
case q(7 downto 4) is
-- 6543210
when "0000" => hex7 <= "1000000"; --0
when "0001" => hex7 <= "1111001"; --1
when "0010" => hex7 <= "0100100"; --2
when "0011" => hex7 <= "0110000"; --3
when "0100" => hex7 <= "0011001"; --4
when "0101" => hex7 <= "0010010"; --5
when "0110" => hex7 <= "0000010"; --6
when "0111" => hex7 <= "1111000"; --7
when "1000" => hex7 <= "0000000"; --8
when "1001" => hex7 <= "0010000"; --9
when "1010" => hex7 <= "0001000"; --10/A
when "1011" => hex7 <= "0000011"; --11/B/b
when "1100" => hex7 <= "1000110"; --12/C
when "1101" => hex7 <= "0100001"; --13/D/d
when "1110" => hex7 <= "0000110"; --14/E
when "1111" => hex7 <= "0001110"; --15/F
when others => hex7 <= "0111111"; -- -
end case;
case q(3 downto 0) is
-- 6543210
when "0000" => hex6 <= "1000000"; --0
when "0001" => hex6 <= "1111001"; --1
when "0010" => hex6 <= "0100100"; --2
when "0011" => hex6 <= "0110000"; --3
when "0100" => hex6 <= "0011001"; --4
when "0101" => hex6 <= "0010010"; --5
when "0110" => hex6 <= "0000010"; --6
when "0111" => hex6 <= "1111000"; --7
when "1000" => hex6 <= "0000000"; --8
when "1001" => hex6 <= "0010000"; --9
when "1010" => hex6 <= "0001000"; --10/A
when "1011" => hex6 <= "0000011"; --11/B/b
when "1100" => hex6 <= "1000110"; --12/C
when "1101" => hex6 <= "0100001"; --13/D/d
when "1110" => hex6 <= "0000110"; --14/E
when "1111" => hex6 <= "0001110"; --15/F
when others => hex6 <= "0111111"; -- -
end case;
end behavior
程序编译时出现如下错误：
Error (10818): Can't infer register for "q[0]" at Counter.vhd(28) because it does not hold its value outside the clock edge I don't know what is means
请帮帮我:(
您的代码包含多个错误：
- 不要使用 Synopsys 包进行算术运算。
使用包numeric_std和类型signedand/orunsigned代替。 q表示状态，会合成为触发器
所以在一个FPGA技术上，初始化它们：:= (others => '0')clear是一个异步信号，所以把它列在敏感列表中。choose是同步信号，所以不要列在敏感列表中。- 当您想添加数字 1、2、3 时，请使用适当的整数文字或将您的文字明确指定为二进制。默认为十进制。
- 使用变量将通过消除重复来缩短代码。
- 清除
q应该通过使用聚合分配所有零来完成：(others => '0'). - for 循环和另一个变量可以进一步减少您的代码并删除另一大段重复代码。
- 用户变量
hex也将删除一个额外的寄存器级，这很可能不是大多数设计者想要的。 - 您评论了 7 段显示器的段名称
6543210，但段通常命名为GFEDCBA。 - 您应该将 7 段解码器放入单独的实体或函数中以提高可重用性。
- 你的7段显示代码是低电平有效，但是设计者应该写出高电平有效的代码。低活性是由于电路板或显示器设计而不是解码器的责任。将
hex赋值给hex7. 时可以进行反转
改进代码如下：
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Counter is
-- ...
end entity;
architecture behavior of Counter is
signal q : unsigned(7 downto 0) := (others => '0');
begin
process(clock, clear)
variable decoded : positive;
variable hex : std_logic_vector(13 downto 0);
begin
case incodec is
when "001" => decoded := 1;
when "011" => decoded := 2;
when "111" => decoded := 3;
when others => decoded := 0;
end case;
if clear = '1' then
q <= (others => '0');
elsif rising_edge(clock) then
if(choose = '1') then -- when choose is '1', the process if for increment
q <= q + decoded;
elsif (choose = '0') then -- when choose is '0', the process if for decrement
q <= q - decoded;
end if;
end if;
for i in 0 to 1 loop
case q(i*4+7 downto i*4) is -- 6543210
when "0000" => hex(i*7+6 downto i*7) := "1000000"; --0
when "0001" => hex(i*7+6 downto i*7) := "1111001"; --1
when "0010" => hex(i*7+6 downto i*7) := "0100100"; --2
when "0011" => hex(i*7+6 downto i*7) := "0110000"; --3
when "0100" => hex(i*7+6 downto i*7) := "0011001"; --4
when "0101" => hex(i*7+6 downto i*7) := "0010010"; --5
when "0110" => hex(i*7+6 downto i*7) := "0000010"; --6
when "0111" => hex(i*7+6 downto i*7) := "1111000"; --7
when "1000" => hex(i*7+6 downto i*7) := "0000000"; --8
when "1001" => hex(i*7+6 downto i*7) := "0010000"; --9
when "1010" => hex(i*7+6 downto i*7) := "0001000"; --10/A
when "1011" => hex(i*7+6 downto i*7) := "0000011"; --11/b
when "1100" => hex(i*7+6 downto i*7) := "1000110"; --12/C
when "1101" => hex(i*7+6 downto i*7) := "0100001"; --13/d
when "1110" => hex(i*7+6 downto i*7) := "0000110"; --14/E
when "1111" => hex(i*7+6 downto i*7) := "0001110"; --15/F
when others => hex(i*7+6 downto i*7) := "0111111"; -- -
end case;
end loop;
hex7 <= hex(13 downto 7);
hex6 <= hex(6 downto 0);
end process;
end architecture;