如何解决"symbol does not have visible declaration error"

how to solve "symbol does not have visible declaration error"

我的vhdl代码如下:

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity pc is
port( inp : in std_logic_vector(31 downto 0);
  oup : out std_logic_vector(31 downto 0));
end pc ;

architecture behv of pc is
signal programcounter : std_logic_vector(31 downto 0);
begin
process(inp)
begin
programcounter<=inp;
oup<=programcounter;
end process;
end behv;

library ieee;
use ieee.std_logic_1164.all;

entity ins_memory is
port( inp1 : in std_logic_vector(31 downto 0);
  oup1 : out std_logic_vector (4 downto 0));

end ins_memory;

architecture behv1 of ins_memory is
type ROM_Array is array (0 to 14)
of std_logic_vector(4 downto 0);
constant Content: ROM_Array := (
0 => "00001",
-- Suppose ROM has
1 => "00010",
-- prestored value
2 => "00011",
-- like this table
3 => "00100",
--
4 => "00101",
--
5 => "00110",
--
6 => "00111",
--
7 => "01000",
--
8 => "01001",
--
9 => "01010",
--
10 => "01011",
--
11 => "01100",
--
12 => "01101",
--
13 => "01110",
--
14 => "01111",
--
OTHERS => "11111"
--
);

component pc is
port( inp : in std_logic_vector(31 downto 0);
  oup : out std_logic_vector(31 downto 0));
end component ;

begin
D1: pc port map(inp1);
process(inp1)
begin
oup1<= Content (to_integer(inp1));
end process;
end behv1;

基本上,我试图在实体 ins_memory 中实例化 pc,它是一个 ROM

我得到的错误是:

oup1<= Content (to_integer(inp1)); The symbol 'TO_INTEGER' does not have a visible declaration.

所以,我该如何解决这个错误?

有两个 entity/architecture 声明,但只有第一个使用 std_logic_arith/unsigned 包,因此第二个不知道。所以在 ins_memory 实体之前添加它:

use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

接下来,to_integer 来自 numeric_std 包。 std_logic_unsigned 包中的 std_logic_vectorinteger 的转换名为 conv_integer,因此更新 oup1 分配给:

oup1<= Content (conv_integer(inp1));

顺便说一句,如果您直接实例化 pc 实体,您可以获得组件声明的脊线:

D1 : entity work.pc port map(inp1);

另一个顺便说一句,考虑使用 VHDL 标准 numeric_std 包而不是专有的 Synopsys std_logic_arith/unsigned 包。