设计编译期间未满足时序要求

Question

我已经创建了一个设计并且想要编译该设计以便为 CPLD 创建一个二进制文件。然而，当我尝试编译设计时，它会输出一条警告，指出未满足时序要求。它似乎在抱怨以下 VHDL 组件，其中外部时钟被划分为设计中其他 VHDL 组件使用的较低时钟频率：

entity clk_divider is
    generic (COUNTER_MAX : integer := 256000);
    port(
            clk_in  : in std_logic;
            reset   : in std_logic;
            clk_out : out std_logic
        );
end clk_divider;    

architecture Behavioral of clk_divider is

    signal signal_level : std_logic := '0';
    signal counter : integer range 0 to COUNTER_MAX := 0;

begin
    clk_divider : process (clk_in, reset)
        begin

        if (reset = '1') then
            signal_level <= '0';
            counter <= 0;
        elsif rising_edge(clk_in) then
            if (counter = COUNTER_MAX) then
                signal_level <= not(signal_level);
                counter <= 0;
            else
                counter <= counter + 1;
            end if;
        end if;
    end process;

    clk_out <= signal_level;
end Behavioral;

设计编译过程中出现的严重警告信息如下所示：

Critical Warning (332012): Synopsys Design Constraints File file not found: 'monitor.sdc'. 
A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. 
Without it, the Compiler will not properly optimize the design.
Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
Info (332105): Deriving Clocks
    Info (332105): create_clock -period 1.000 -name clk clk
    Info (332105): create_clock -period 1.000 -name clk_divider:clk_module|signal_level clk_divider:clk_module|signal_level
Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
Info: Can't run Report Timing Closure Recommendations. The current device family is not supported.
Critical Warning (332148): Timing requirements not met
Info (332146): Worst-case setup slack is -7.891
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):    -7.891            -123.541 clk 
    Info (332119):    -1.602              -5.110 clk_divider:clk_module|signal_level 
Info (332146): Worst-case hold slack is -0.816
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):    -0.816              -0.816 clk 
    Info (332119):     1.732               0.000 clk_divider:clk_module|signal_level 
Info (332146): Worst-case recovery slack is -4.190
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):    -4.190             -20.950 clk_divider:clk_module|signal_level 
    Info (332119):    -3.654             -76.734 clk 
Info (332146): Worst-case removal slack is 4.320
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):     4.320               0.000 clk 
    Info (332119):     4.856               0.000 clk_divider:clk_module|signal_level 
Info (332146): Worst-case minimum pulse width slack is -2.289
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):    -2.289              -2.289 clk 
    Info (332119):     0.247               0.000 clk_divider:clk_module|signal_level 
Info (332001): The selected device family is not supported by the report_metastability command.
Info (332102): Design is not fully constrained for setup requirements
Info (332102): Design is not fully constrained for hold requirements

出现此警告消息的原因是什么，我该如何解决？另外，松弛数字对我的设计有何影响？

Answer 1

由于无法找到 monitor.sdc，只要日志显示以下约束，Quartus 就会尝试以 1GHz（周期=1ns）合成您的电路。

create_clock -period 1.000 -name clk clk
create_clock -period 1.000 -name clk_divider:clk_module|signal_level clk_divider:clk_module|signal_level

第一行是clk端口（必须在顶层module/entity），第二行是signal_level信号。您可以适当修改周期并将约束放入monitor.sdc。然后你应该将该文件添加到项目中。

松弛值告诉您目标值与实际值之间的差异。如果路径满足时序要求，则它具有正的松弛度。如果不满足，则松弛为负。

您的目标时钟周期是 1ns，但关键（最差）路径的松弛时间为 -7.891ns。实际可达到的周期可计算如下。

actual period = target period - setup slack = 1.000 - (-7.891) = 8.891ns

根据上面的结果，8.9ns 是 clk 可以达到的周期。我也会尝试较小的值，但如果您的实际输入时钟 (clk) 不快于 100MHz，则没有必要。

signal_level的周期取决于COUNTER_MAX的最小值。实际上电路的其余部分似乎已经比 clk_divider 模块快，因为 signal_level 的松弛 (-1.602) 更好。可以设置与clk.

相同的周期

设计编译期间未满足时序要求

Timing requirement not met during design compilation

timing

clock

fpga

intel-fpga

quartus