使用 VHDL/ModelSim 中的配置规范
Using configuration specification in VHDL/ModelSim
我正在尝试使用 VHDL 配置规范来预设
这应该是可行的，如 IEEE1076-2008, section 7.3.2.1 所示，其中给出了以下示例：
entity AND_GATE is
generic (I1toO, I2toO: DELAY_LENGTH := 4 ns);
port (I1, I2: in BIT; O: out BIT);
end entity AND_GATE;
entity XOR_GATE is
generic (I1toO, I2toO: DELAY_LENGTH := 4 ns);
port (I1, I2: in BIT; O: out BIT);
end entity XOR_GATE;
package MY_GATES is
component AND_GATE is
generic (I1toO, I2toO: DELAY_LENGTH := 4 ns);
port (I1, I2: in BIT; O: out BIT);
end component AND_GATE;
component XOR_GATE is
generic (I1toO, I2toO: DELAY_LENGTH := 4 ns);
port (I1, I2: in BIT; O: out BIT);
end component XOR_GATE;
end package MY_GATES;
entity Half_Adder is
port (X, Y: in BIT; Sum, Carry: out BIT);
end entity Half_Adder;
use WORK.MY_GATES.all;
architecture Structure of Half_Adder is
for L1: XOR_GATE use
entity WORK.XOR_GATE(Behavior) -- The primary binding
generic map (3 ns, 3 ns) -- indication for instance L1.
port map (I1 => I1, I2 => I2, O => O);
for L2: AND_GATE use
entity WORK.AND_GATE(Behavior) -- The primary binding
generic map (3 ns, 4 ns) -- indication for instance L2.
port map (I1, open, O);
begin
L1: XOR_GATE port map (X, Y, Sum);
L2: AND_GATE port map (X, Y, Carry);
end architecture Structure;
use WORK.GLOBAL_SIGNALS.all;
configuration Different of Half_Adder is
for Structure
for L1: XOR_GATE
generic map (2.9 ns, 3.6 ns); -- The incremental binding
end for; -- indication of L1; rebinds its generics.
for L2: AND_GATE
generic map (2.8 ns, 3.25 ns) -- The incremental binding
port map (I2 => Tied_High); -- indication of L2; rebinds
end for; -- its generics and binds its open port.
end for;
end configuration Different;
即使我自己添加示例中缺少的包
package GLOBAL_SIGNALS is
constant Tied_High : bit := '1';
end package GLOBAL_SIGNALS;
在 Modelsim 中的细化仍然失败。
Error: [...]/half_adder.vhd(36): (vcom-1035) Formal port "I2" has OPEN or no actual associated with it.
线路原因
port map (I1, open, O);
这似乎已经表明 Modelsim 没有正确支持这些配置语句。
我想使用这个配置规范来简化我的设计输入。
示例：
entity comp is
generic(step : time; defined: boolean);
port(clk, data : in bit);
end entity;
entity e is end entity e;
architecture a of e is
component comp is
generic(step : time; defined: boolean);
port(clk, data : in bit);
end component;
signal clk1, clk2 : bit;
for a : comp use
entity work.comp
generic map(step => 1 ns)
port map(clk => clk1);
for b : comp use
entity work.comp
generic map(step => 100 ns)
port map(clk => clk2);
for all : comp use
entity work.comp
generic map(defined => true);
signal sig_a, sig_b : bit;
begin
a: comp
port map(data => sig_a);
b_gen : for i in 0 to 2 generate
b: comp
port map(data => sig_b);
end generate;
end architecture;
此代码抛出大量错误：
Error: [...]/e.vhd(19): (vcom-1031) Formal generic "defined" has OPEN or no actual associated with it.
Error: [...]/e.vhd(19): (vcom-1035) Formal port "data" has OPEN or no actual associated with it.
Error: [...]/e.vhd(23): (vcom-1031) Formal generic "defined" has OPEN or no actual associated with it.
Error: [...]/e.vhd(23): (vcom-1035) Formal port "data" has OPEN or no actual associated with it.
Error: [...]/e.vhd(26): (vcom-1031) Formal generic "step" has OPEN or no actual associated with it.
Error: [...]/e.vhd(24): ALL configuration specification for component "comp" attempts to re-bind instances already bound.
Error: [...]/e.vhd(24): ALL configuration specification for component "comp" attempts to re-bind instances already bound.
Error: [...]/e.vhd(32): (vcom-1031) Formal generic "step" has OPEN or no actual associated with it.
Error: [...]/e.vhd(32): (vcom-1031) Formal generic "defined" has OPEN or no actual associated with it.
Error: [...]/e.vhd(32): (vcom-1035) Formal port "clk" has OPEN or no actual associated with it.
Error: [...]/e.vhd(36): (vcom-1031) Formal generic "step" has OPEN or no actual associated with it.
Error: [...]/e.vhd(36): (vcom-1031) Formal generic "defined" has OPEN or no actual associated with it.
Error: [...]/e.vhd(36): (vcom-1035) Formal port "clk" has OPEN or no actual associated with it.
Warning: [...]/e.vhd(24): (vcom-1263) Configuration specification "all : comp" applies to no component instantiation statements.
Error: [...]/e.vhd(20): No statement with label "b" was found.
看来这不是使用配置规范的受支持方式。太糟糕了，因为它会简化我的设计入门。
我这只是一个 Modelsim 错误，或者配置规范永远不会以这种方式帮助这些默认绑定？
问题变了，答案也变了。
在 Modelsim 中的细化仍然失败。
Error: [...]/half_adder.vhd(36): (vcom-1035) Formal port "I2" has OPEN or no actual associated with it.
线路原因
port map (I1, open, O);
这似乎已经表明 Modelsim 没有正确支持这些配置语句。
没有'properly'可以应用于您的结论，VHDL标准不支持。
错误似乎是由于在未绑定 I2 时试图详细说明 Half_Adder 引起的。配置规范将 I2 与 open 关联，这是不允许的。
如果创建 Minimal, Complete and Verifiable example:
-- IEEE Std 1076-1993 5.2.1 Binding Indication (example)
-- -2008 7.3.2.1
package global_signals is -- THIS PACKAGE MISSING IN THE EXAMPLE
signal Tied_High: bit := '1';
end package;
entity AND_GATE is -- ADDED entity and architecture
generic (I1toO, I2toO: DELAY_LENGTH := 4 ns);
port (I1, I2: in BIT; O: out BIT);
end entity AND_GATE;
architecture Behavior of AND_GATE is -- ADDED
signal In1, In2: BIT;
begin
In1 <= I1 after I1toO;
In2 <= I2 after I2toO;
O <= In1 and In2;
process
begin
report
LF & HT & "I1to0 = " & time'image(I1toO) &
LF & HT & "I2to0 = " & time'image(I2toO);
wait;
end process;
end architecture Behavior;
entity XOR_GATE is -- ADDED entity and architecture
generic (I1toO, I2toO : DELAY_LENGTH := 4 ns);
port (I1, I2: in BIT; O : out BIT);
end entity XOR_GATE;
architecture Behavior of XOR_GATE is -- ADDED
signal In1, In2: BIT;
begin
In1 <= I1 after I1toO;
In2 <= I2 after I2toO;
O <= In1 xor In2;
process
begin
report
LF & HT & "I1to0 = " & time'image(I1toO) &
LF & HT & "I2to0 = " & time'image(I2toO);
wait;
end process;
end architecture Behavior;
package MY_GATES is
component AND_GATE is
generic (I1toO, I2toO: DELAY_LENGTH := 4 ns);
port (I1, I2: in BIT; O: out BIT);
end component AND_GATE;
component XOR_GATE is
generic (I1toO, I2toO: DELAY_LENGTH := 4 ns);
port (I1, I2: in BIT; O : out BIT);
end component XOR_GATE;
end package MY_GATES;
entity Half_Adder is
port (X, Y: in BIT;
Sum, Carry: out BIT);
end entity Half_Adder;
use WORK.MY_GATES.all;
architecture Structure of Half_Adder is
signal O: bit; -- Added
for L1: XOR_GATE use
entity WORK.XOR_GATE(Behavior) -- The primary binding indication
generic map (3 ns, 3 ns) -- for instance L1.
port map (I1 => I1, I2 => I2, O => O);
for L2: AND_GATE use
entity WORK.AND_GATE(Behavior) -- The primary binding indication
-- generic map (3 ns, 4 ns) -- for instance L2.
port map (I1, open, O);
begin
L1: XOR_GATE port map (X, Y, Sum);
L2: AND_GATE port map (X, Y, Carry);
end architecture Structure;
use WORK.GLOBAL_SIGNALS.all;
configuration Different of Half_Adder is
for Structure
for L1: XOR_GATE
generic map (2.9 ns, 3.6 ns); -- The incremental binding
end for; -- indication of L1; rebinds its generics.
for L2: AND_GATE
generic map (2.8 ns, 3.25 ns) -- The incremental binding
port map (I2 => Tied_High); -- indication L2; rebinds its generics
end for; -- and binds its open port.
end for;
end configuration Different;
在这种情况下，它在一个设计文件中分析、阐述和模拟：
ghdl -a Half_Adder.vhdl
ghdl -e different
ghdl -r different
Half_Adder.vhdl:44:9:@0ms:(report note):
I1to0 = 2900000 fs
I2to0 = 3600000 fs
Half_Adder.vhdl:22:9:@0ms:(report note):
I1to0 = 2800000 fs
I2to0 = 3250000 fs
同时演示代码中表达的增量绑定功能是否正常。
请注意，这需要从包含最近 Github 提交的源代码构建的 ghdl 实现。
提交：9e0cf4af3cf2141002b37db9803c15afec8ea2f4 [9e0cf4a]
Parents : b801510561
作者 : 特里斯坦金戈尔德
日期：2017 年 10 月 30 日 7:19:41 上午 GMT+13
分析、阐述和运行上述Half_Adder需要一个在2017年10月30日之后从Github存储库构建的ghdl，增量绑定的能力在更改中意外丢失最近恢复了语义分析的应用方式。该功能将在 ghdl-0.35 中发布。
几年来没有人注意到这种缺失。该功能可能不像增量绑定的作者所希望的那样受到热烈欢迎。您还可能注意到标准中的示例不完整，并且在以后的修订版中出现了其他拼写错误。 MCVe 现已合并到 ghdl 的测试套件中。
您生成的第二个示例代码 (e.vhdl) 未提供配置声明。
Annex I (Informative) Glossary
incremental binding: A binding indication in a configuration declaration that either reassociates a previously associated local generic constant or that associates a previously unassociated local port is said to incrementally rebind the component instance or instances to which the binding indication applies. (7.3.2.1)
这个'restriction'是如何产生的是语义要求的问题。
可以从 Jean-Michel Bergé、Alain Fonkoua、Serge Maginot 和 Jacques Rouillard 的“VHDL'92”一书中的作者那里了解增量绑定。请参阅 VHDL'92，6。增量绑定，第 47 页到第 56 页。
（增量绑定也可以在 IEEE Std P1076-1992c 中找到，随后被纳入 IEEE Std 1076-1993 修订版）。
你的第二个例子中存在各种语义缺陷：
e.vhdl:
entity comp is
generic(step : time; defined: boolean);
port(clk, data : in bit);
end entity;
entity e is end entity e;
architecture a of e is
component comp is
generic(step : time; defined: boolean);
port(clk, data : in bit);
end component;
signal clk1, clk2 : bit;
for a : comp use -- Line 15
entity work.comp
generic map(step => 1 ns)
port map(clk => clk1);
for b : comp use -- Line 20
entity work.comp
generic map(step => 100 ns)
port map(clk => clk2);
for all : comp use -- Line 24
entity work.comp
generic map(defined => true);
signal sig_a, sig_b : bit;
begin
a: comp -- Line 31
port map(data => sig_a);
b_gen : for i in 0 to 2 generate
b: comp -- Line 35
port map(data => sig_b);
end generate;
end architecture;
除了缺少配置声明外，该示例还通过 Modelsim 错误和警告以及 ghdl 演示了这些缺点：
ghdl -a e.vhdl
e.vhdl:31:5:error: no actual for constant interface "step"
e.vhdl:35:9:error: no actual for constant interface "step"
e.vhdl:20:9:error: no component instantation with label "b"
e.vhdl:24:5:error: component instance "a" is already bound by a configuration specification
e.vhdl:16:5:error: (previous is configuration specification)
ghdl:error: compilation error
综合工具通常支持配置规范但不支持配置声明。当应用于针对硅的设计时，增量绑定没有实际用途。
我正在尝试使用 VHDL 配置规范来预设
这应该是可行的，如 IEEE1076-2008, section 7.3.2.1 所示，其中给出了以下示例：
entity AND_GATE is
generic (I1toO, I2toO: DELAY_LENGTH := 4 ns);
port (I1, I2: in BIT; O: out BIT);
end entity AND_GATE;
entity XOR_GATE is
generic (I1toO, I2toO: DELAY_LENGTH := 4 ns);
port (I1, I2: in BIT; O: out BIT);
end entity XOR_GATE;
package MY_GATES is
component AND_GATE is
generic (I1toO, I2toO: DELAY_LENGTH := 4 ns);
port (I1, I2: in BIT; O: out BIT);
end component AND_GATE;
component XOR_GATE is
generic (I1toO, I2toO: DELAY_LENGTH := 4 ns);
port (I1, I2: in BIT; O: out BIT);
end component XOR_GATE;
end package MY_GATES;
entity Half_Adder is
port (X, Y: in BIT; Sum, Carry: out BIT);
end entity Half_Adder;
use WORK.MY_GATES.all;
architecture Structure of Half_Adder is
for L1: XOR_GATE use
entity WORK.XOR_GATE(Behavior) -- The primary binding
generic map (3 ns, 3 ns) -- indication for instance L1.
port map (I1 => I1, I2 => I2, O => O);
for L2: AND_GATE use
entity WORK.AND_GATE(Behavior) -- The primary binding
generic map (3 ns, 4 ns) -- indication for instance L2.
port map (I1, open, O);
begin
L1: XOR_GATE port map (X, Y, Sum);
L2: AND_GATE port map (X, Y, Carry);
end architecture Structure;
use WORK.GLOBAL_SIGNALS.all;
configuration Different of Half_Adder is
for Structure
for L1: XOR_GATE
generic map (2.9 ns, 3.6 ns); -- The incremental binding
end for; -- indication of L1; rebinds its generics.
for L2: AND_GATE
generic map (2.8 ns, 3.25 ns) -- The incremental binding
port map (I2 => Tied_High); -- indication of L2; rebinds
end for; -- its generics and binds its open port.
end for;
end configuration Different;
即使我自己添加示例中缺少的包
package GLOBAL_SIGNALS is
constant Tied_High : bit := '1';
end package GLOBAL_SIGNALS;
在 Modelsim 中的细化仍然失败。
Error: [...]/half_adder.vhd(36): (vcom-1035) Formal port "I2" has OPEN or no actual associated with it.
线路原因
port map (I1, open, O);
这似乎已经表明 Modelsim 没有正确支持这些配置语句。
我想使用这个配置规范来简化我的设计输入。
示例：
entity comp is
generic(step : time; defined: boolean);
port(clk, data : in bit);
end entity;
entity e is end entity e;
architecture a of e is
component comp is
generic(step : time; defined: boolean);
port(clk, data : in bit);
end component;
signal clk1, clk2 : bit;
for a : comp use
entity work.comp
generic map(step => 1 ns)
port map(clk => clk1);
for b : comp use
entity work.comp
generic map(step => 100 ns)
port map(clk => clk2);
for all : comp use
entity work.comp
generic map(defined => true);
signal sig_a, sig_b : bit;
begin
a: comp
port map(data => sig_a);
b_gen : for i in 0 to 2 generate
b: comp
port map(data => sig_b);
end generate;
end architecture;
此代码抛出大量错误：
Error: [...]/e.vhd(19): (vcom-1031) Formal generic "defined" has OPEN or no actual associated with it.
Error: [...]/e.vhd(19): (vcom-1035) Formal port "data" has OPEN or no actual associated with it.
Error: [...]/e.vhd(23): (vcom-1031) Formal generic "defined" has OPEN or no actual associated with it.
Error: [...]/e.vhd(23): (vcom-1035) Formal port "data" has OPEN or no actual associated with it.
Error: [...]/e.vhd(26): (vcom-1031) Formal generic "step" has OPEN or no actual associated with it.
Error: [...]/e.vhd(24): ALL configuration specification for component "comp" attempts to re-bind instances already bound.
Error: [...]/e.vhd(24): ALL configuration specification for component "comp" attempts to re-bind instances already bound.
Error: [...]/e.vhd(32): (vcom-1031) Formal generic "step" has OPEN or no actual associated with it.
Error: [...]/e.vhd(32): (vcom-1031) Formal generic "defined" has OPEN or no actual associated with it.
Error: [...]/e.vhd(32): (vcom-1035) Formal port "clk" has OPEN or no actual associated with it.
Error: [...]/e.vhd(36): (vcom-1031) Formal generic "step" has OPEN or no actual associated with it.
Error: [...]/e.vhd(36): (vcom-1031) Formal generic "defined" has OPEN or no actual associated with it.
Error: [...]/e.vhd(36): (vcom-1035) Formal port "clk" has OPEN or no actual associated with it.
Warning: [...]/e.vhd(24): (vcom-1263) Configuration specification "all : comp" applies to no component instantiation statements.
Error: [...]/e.vhd(20): No statement with label "b" was found.
看来这不是使用配置规范的受支持方式。太糟糕了，因为它会简化我的设计入门。
我这只是一个 Modelsim 错误，或者配置规范永远不会以这种方式帮助这些默认绑定？
问题变了，答案也变了。
在 Modelsim 中的细化仍然失败。
Error: [...]/half_adder.vhd(36): (vcom-1035) Formal port "I2" has OPEN or no actual associated with it.
线路原因
port map (I1, open, O);
这似乎已经表明 Modelsim 没有正确支持这些配置语句。
没有'properly'可以应用于您的结论，VHDL标准不支持。
错误似乎是由于在未绑定 I2 时试图详细说明 Half_Adder 引起的。配置规范将 I2 与 open 关联，这是不允许的。
如果创建 Minimal, Complete and Verifiable example:
-- IEEE Std 1076-1993 5.2.1 Binding Indication (example)
-- -2008 7.3.2.1
package global_signals is -- THIS PACKAGE MISSING IN THE EXAMPLE
signal Tied_High: bit := '1';
end package;
entity AND_GATE is -- ADDED entity and architecture
generic (I1toO, I2toO: DELAY_LENGTH := 4 ns);
port (I1, I2: in BIT; O: out BIT);
end entity AND_GATE;
architecture Behavior of AND_GATE is -- ADDED
signal In1, In2: BIT;
begin
In1 <= I1 after I1toO;
In2 <= I2 after I2toO;
O <= In1 and In2;
process
begin
report
LF & HT & "I1to0 = " & time'image(I1toO) &
LF & HT & "I2to0 = " & time'image(I2toO);
wait;
end process;
end architecture Behavior;
entity XOR_GATE is -- ADDED entity and architecture
generic (I1toO, I2toO : DELAY_LENGTH := 4 ns);
port (I1, I2: in BIT; O : out BIT);
end entity XOR_GATE;
architecture Behavior of XOR_GATE is -- ADDED
signal In1, In2: BIT;
begin
In1 <= I1 after I1toO;
In2 <= I2 after I2toO;
O <= In1 xor In2;
process
begin
report
LF & HT & "I1to0 = " & time'image(I1toO) &
LF & HT & "I2to0 = " & time'image(I2toO);
wait;
end process;
end architecture Behavior;
package MY_GATES is
component AND_GATE is
generic (I1toO, I2toO: DELAY_LENGTH := 4 ns);
port (I1, I2: in BIT; O: out BIT);
end component AND_GATE;
component XOR_GATE is
generic (I1toO, I2toO: DELAY_LENGTH := 4 ns);
port (I1, I2: in BIT; O : out BIT);
end component XOR_GATE;
end package MY_GATES;
entity Half_Adder is
port (X, Y: in BIT;
Sum, Carry: out BIT);
end entity Half_Adder;
use WORK.MY_GATES.all;
architecture Structure of Half_Adder is
signal O: bit; -- Added
for L1: XOR_GATE use
entity WORK.XOR_GATE(Behavior) -- The primary binding indication
generic map (3 ns, 3 ns) -- for instance L1.
port map (I1 => I1, I2 => I2, O => O);
for L2: AND_GATE use
entity WORK.AND_GATE(Behavior) -- The primary binding indication
-- generic map (3 ns, 4 ns) -- for instance L2.
port map (I1, open, O);
begin
L1: XOR_GATE port map (X, Y, Sum);
L2: AND_GATE port map (X, Y, Carry);
end architecture Structure;
use WORK.GLOBAL_SIGNALS.all;
configuration Different of Half_Adder is
for Structure
for L1: XOR_GATE
generic map (2.9 ns, 3.6 ns); -- The incremental binding
end for; -- indication of L1; rebinds its generics.
for L2: AND_GATE
generic map (2.8 ns, 3.25 ns) -- The incremental binding
port map (I2 => Tied_High); -- indication L2; rebinds its generics
end for; -- and binds its open port.
end for;
end configuration Different;
在这种情况下，它在一个设计文件中分析、阐述和模拟：
ghdl -a Half_Adder.vhdl
ghdl -e different
ghdl -r different
Half_Adder.vhdl:44:9:@0ms:(report note): I1to0 = 2900000 fs I2to0 = 3600000 fs Half_Adder.vhdl:22:9:@0ms:(report note): I1to0 = 2800000 fs I2to0 = 3250000 fs
同时演示代码中表达的增量绑定功能是否正常。
请注意，这需要从包含最近 Github 提交的源代码构建的 ghdl 实现。
提交：9e0cf4af3cf2141002b37db9803c15afec8ea2f4 [9e0cf4a]
Parents : b801510561
作者 : 特里斯坦金戈尔德
日期：2017 年 10 月 30 日 7:19:41 上午 GMT+13
分析、阐述和运行上述Half_Adder需要一个在2017年10月30日之后从Github存储库构建的ghdl，增量绑定的能力在更改中意外丢失最近恢复了语义分析的应用方式。该功能将在 ghdl-0.35 中发布。
几年来没有人注意到这种缺失。该功能可能不像增量绑定的作者所希望的那样受到热烈欢迎。您还可能注意到标准中的示例不完整，并且在以后的修订版中出现了其他拼写错误。 MCVe 现已合并到 ghdl 的测试套件中。
您生成的第二个示例代码 (e.vhdl) 未提供配置声明。
Annex I (Informative) Glossary
incremental binding: A binding indication in a configuration declaration that either reassociates a previously associated local generic constant or that associates a previously unassociated local port is said to incrementally rebind the component instance or instances to which the binding indication applies. (7.3.2.1)
这个'restriction'是如何产生的是语义要求的问题。
可以从 Jean-Michel Bergé、Alain Fonkoua、Serge Maginot 和 Jacques Rouillard 的“VHDL'92”一书中的作者那里了解增量绑定。请参阅 VHDL'92，6。增量绑定，第 47 页到第 56 页。
（增量绑定也可以在 IEEE Std P1076-1992c 中找到，随后被纳入 IEEE Std 1076-1993 修订版）。
你的第二个例子中存在各种语义缺陷：
e.vhdl:
entity comp is
generic(step : time; defined: boolean);
port(clk, data : in bit);
end entity;
entity e is end entity e;
architecture a of e is
component comp is
generic(step : time; defined: boolean);
port(clk, data : in bit);
end component;
signal clk1, clk2 : bit;
for a : comp use -- Line 15
entity work.comp
generic map(step => 1 ns)
port map(clk => clk1);
for b : comp use -- Line 20
entity work.comp
generic map(step => 100 ns)
port map(clk => clk2);
for all : comp use -- Line 24
entity work.comp
generic map(defined => true);
signal sig_a, sig_b : bit;
begin
a: comp -- Line 31
port map(data => sig_a);
b_gen : for i in 0 to 2 generate
b: comp -- Line 35
port map(data => sig_b);
end generate;
end architecture;
除了缺少配置声明外，该示例还通过 Modelsim 错误和警告以及 ghdl 演示了这些缺点：
ghdl -a e.vhdl e.vhdl:31:5:error: no actual for constant interface "step" e.vhdl:35:9:error: no actual for constant interface "step" e.vhdl:20:9:error: no component instantation with label "b" e.vhdl:24:5:error: component instance "a" is already bound by a configuration specification e.vhdl:16:5:error: (previous is configuration specification) ghdl:error: compilation error
综合工具通常支持配置规范但不支持配置声明。当应用于针对硅的设计时，增量绑定没有实际用途。