iverilog testbench error: input is declared as wire, but it isn't

Question

我是 iverilog 的新手，我正在创建一个计数器以将 100Mhz 时钟频率降低到更容易使用的频率，这是一个更大项目的一部分。我发现了一些代码可以做到这一点，所以我尝试为它编写一个测试平台。这是我找到的代码：

    module slowClock(clk, reset, clk_1Hz);
input clk, reset;
output clk_1Hz;

reg clk_1Hz;
reg [27:0] counter;

always@(posedge reset or posedge clk)
begin
     if (reset == 1'b1)
         begin
             clk_1Hz <= 0;
             counter <= 0;
         end
     else
         begin
             counter <= counter + 1;
             if ( counter == 25_000_000)
                 begin
                     counter <= 0;
                     clk_1Hz <= ~clk_1Hz;
                 end
         end
end
endmodule

这里是我写的测试平台：

module slowClock_tb(clk, reset, clk_1Hz);
    input  clk;
    input  reset;
    output  clk_1Hz;

initial 
begin
    clk = 1'b0; 
    reset = 1'b0;
#2 reset = ~reset;

end

    always #3 clk = ~clk;

slowClock clock_generator(clk, reset, clk_1Hz);


endmodule

错误信息如下：

$ iverilog  slowClock.v slowClock_tb.v 
slowClock_tb.v:8: error: clk is not a valid l-value in slowClock_tb.
slowClock_tb.v:2:      : clk is declared here as wire.
slowClock_tb.v:9: error: reset is not a valid l-value in slowClock_tb.
slowClock_tb.v:3:      : reset is declared here as wire.
slowClock_tb.v:10: error: reset is not a valid l-value in slowClock_tb.
slowClock_tb.v:3:      : reset is declared here as wire.
slowClock_tb.v:14: error: clk is not a valid l-value in slowClock_tb.
slowClock_tb.v:2:      : clk is declared here as wire.
4 error(s) during elaboration.

第一条错误信息：clk在这里声明为wire。但它在原始代码或测试平台中都没有被声明为电线。重置也一样。我曾尝试从校内导师那里获得帮助，但他们不知道为什么会这样，也不知道如何解决。

有人可以建议如何解决这个问题吗？

Answer 1

当您不包含类型时，所有 variables/signals 都被推断为连线。你没有给他们一个类型，所以他们被认为是电线。

您还在测试台模块中将 clk 和 reset 定义为输入，但随后您在测试台内分配给它们，所以这就是它们不是有效左值的原因.

试试这个：

module slowClock(
    input  wire clk,
    input  wire reset,
    output reg clk_1Hz
    );

    reg [27:0] counter;

    always@(posedge reset or posedge clk) begin
        if (reset == 1'b1) begin
            clk_1Hz <= 0;
            counter <= 0;
        end else begin
            counter <= counter + 1;
            if ( counter == 25_000_000) begin
                counter <= 0;
                clk_1Hz <= ~clk_1Hz;
            end
        end
    end
endmodule

module slowClock_tb;
    reg clk = 1'b0;
    reg reset = 1'b0;
    integer counter = 0;
    wire clk_1Hz;

    initial begin
        #2 reset <= ~reset;
    end

    always #3 clk <= ~clk;

    slowClock clock_generator(clk, reset, clk_1Hz);

    always @(posedge clk) begin
        counter <= counter + 1;
        $display("%0d", counter);

        if (counter > 100) $finish;
    end

endmodule

iverilog testbench error: input is declared as wire, but it isn't

iverilog testbench error: input is declared as wire, but it isn't

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