如何将一个模块的输出信号连接到另一个模块的输入信号

Question

假设我的VHDL代码是这样的：

entity x1:
port(a: out std_logic;
....
....
);
architecture behv1 of x1 is
....
end behv1;

entity y1 
port(b: in std_logic;
....
....
);
architecture behv1 of y1 is
begin
m1: x1 port map(a=>b);    
end behv1;

所以，这里的 a 是实体 x1 的输出信号，它直接连接到另一个实体 y1 的输入 b。

Answer 1

你有点走错路了。

entity y1 提供 y1 实体的接口。它指定您有实体的输入 b。这意味着您可以从 architecture 声明中读取 b 的值。然后，您应该在 architecture behav1.

中实现您希望 y1 模块执行的操作

不过据我了解，您想实例化一个 x1 和一个 y1，然后将它们连接在一起。为此，您需要提供 x1 和 y1 的实现，然后在单独的顶层实例化两者并将它们连接在一起。像这样：

entity x1:
port(a: out std_logic;
....
....
);
architecture behv1 of x1 is
    -- Do something...
end behv1;

entity y1 
port(b: in std_logic;
....
....
);
architecture behv1 of y1 is
begin
    -- Do something...    
end behv1;

entity toplevel
port (
    clk : in std_logic;
    ...
);
architecture toplevel_arch of toplevel is
    signal x1_output : std_logic; -- Temp to connect both modules
begin
    m_x1: x1 port map(a => x1_output);
    m_y1: y1 port map(b => x1_output);
end toplevel_arch;

Answer 2

下面举例分析、阐述和模拟

它说明了如何分层连接输入和输出。

library ieee;
use ieee.std_logic_1164.all;

entity x3 is
    port (
        x3in:   in  std_logic;
        x3out:  out std_logic
    );
end entity;

architecture behv3 of x3 is
begin
    x3out <= x3in;
end architecture;

library ieee;
use ieee.std_logic_1164.all;

entity y3 is
    port (
        y3in:   in  std_logic;
        y3out:  out std_logic
    );
end entity;

architecture behv3 of y3 is
begin   
    y3out <= y3in;
end architecture;

library ieee;
use ieee.std_logic_1164.all;
entity z3 is
    port (
        z3in:   in  std_logic;
        z3out:  out std_logic
    );
end entity;

architecture foo of z3 is

    component x3 is
        port (
            x3in:   in  std_logic;
            x3out:  out std_logic
        );
    end component;

    component y3 is
        port (
            y3in:   in  std_logic;
            y3out:  out std_logic
        );
    end component;

    signal x3out:   std_logic;

begin
u0:
    x3 
        port map ( 
            x3in => z3in,
            x3out => x3out
        );
u1:
    y3 
        port map ( 
            y3in => x3out,
            y3out => z3out
        );
end architecture;

可在语言参考手册 (LRM)、IEEE Std 1076-2008 6.5.6.3 端口条款中找到适用规则：

After a given description is completely elaborated (see Clause 14), if a formal port is associated with an actual that is itself a port, then the following restrictions apply depending upon the mode (see 6.5.2), if any, of the formal port:

a) For a formal port of mode in, the associated actual shall be a port of mode in, out, inout, or buffer. This restriction applies both to an actual that is associated as a name in the actual part of an association element and to an actual that is associated as part of an expression in the actual part of an association element.
b) For a formal port of mode out, the associated actual shall be a port of mode out, inout, or buffer.
c) For a formal port of mode inout, the associated actual shall be a port of mode out, inout, or buffer.
d) For a formal port of mode buffer, the associated actual shall be a port of mode out, inout, or buffer.
e) For a formal port of mode linkage, the associated actual may be a port of any mode.

如何将一个模块的输出信号连接到另一个模块的输入信号

how to connect output signal of one module to input signal of other module

vhdl