Verilog：原语或连续赋值

Question

我是运行这个代码

module neuron_xor(x0, x1, y4);
    input signed [4:0] x0, x1;
    reg signed [4:0] w02, w03, w12, w13, w24, w34;
    reg signed [4:0] th2, th3, th4;
    wire signed [4:0] y2, y3;
    output signed [4:0] y4;

    neuron n2(x0, x1, w02, w12, th2, y2);
    neuron n3(x0, x1, w03, w13, th3, y3);

    neuron n4(y2, y3, w24, w34, th4, y4);

    initial begin
    w02 = 2; w03 = -2;
    w12 = 2; w13 = -2;
    w24 = 2; w34 = 2;

    th2 = 1; th3 = -3; th4 = 3;
    end
endmodule

有了这个测试平台：

`timescale 1ns/100ps

module tb_neuron_xor();

    reg signed [4:0] x0, x1;
    reg signed [4:0] w02, w03, w12, w13, w24, w34;
    reg signed [4:0] th2, th3, th4;
    wire signed [4:0] y2, y3;
    wire signed [4:0] y4;
    reg signed [4:0] ctrl;
    integer i, j, flag;

    neuron n2(x0, x1, w02, w12, th2, y2);
    neuron n3(x0, x1, w03, w13, th3, y3);
    neuron n4(y2, y3, w24, w34, th4, y4);

    initial begin

        $dumpfile("tb_neu_xor.vcd");
        $dumpvars;

        flag = 0;

        #10;
        for (i = -16; i < 15; i = i + 1) begin
            for (j = -16; j < 15; j = j + 1) begin

                x0 = i; x1 = j;
                ctrl = x0 ^ x1;

                if (ctrl != y4) begin
                    flag = 1;
                    $display("Error: x0=%b, x1=%b, y4=%b, ctrl=%b", x0,x1,y4,ctrl);
                end
                $display("y4=%d, ctrl=%d", y4, ctrl);
            end
        end

        if (flag == 0) begin
            $display("No Error!");
        end

        #10;
        $finish;

    end
endmodule

我每次迭代都得到 y4=X。据我了解，发生这种情况是因为没有为 y4 赋予初始值，默认值为 X。但是，我无法将 y4 的类型更改为 reg 以便为其赋值。这将导致在测试台第 15 行，神经元 n4 中显示一条错误消息：

tb_neuron_xor.v:15: error: reg y4; cannot be driven by primitives or continuous assignment. tb_neuron_xor.v:15: error: Output port expression must support continuous assignment. tb_neuron_xor.v:15: : Port y0 of neuron is connected to y4

我该如何解决这个问题？

如果需要更好的上下文，神经元模块的定义如下：

module neuron(x0, x1, w0, w1, th0, y0);
    input signed [4:0] x0, x1; 
    input signed [4:0] w0, w1;
    input signed [4:0] th0;
    output reg signed [4:0] y0;

    reg signed [11:0] a0, a1, a2;

    always @(x0 or x1 or w0 or w1 or th0)
    begin
        a0 = x0*w0;
        a1 = x1*w1;
        a2 = a0 + a1;

        if (a2 >= th0)
            y0 = 1;
        else
            y0 = 0;
    end

endmodule

Answer 1

为什么不将默认值分配给 neuron() 的 y0？

output reg signed [4:0] y0=0;

我还建议您对 regs 使用重置，并在模拟开始时重置它们。

Verilog：原语或连续赋值

Verilog: primitives or continuous assignment

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