在verilog，Modelsim中制作计数器

Question

我正在尝试在 verilog 中制作循环计数器

module rr_arbiter (
clk, // positive edge trigger
reset,  // negative edge trigger
req0, req1, req2, req3, 
grant0, grant1, grant2, grant3,
priority, priority_req);

input clk, reset;
input req0, req1, req2, req3;
input priority;
input [1:0] priority_req;

output grant0, grant1, grant2, grant3;  

reg x 

always(posedge clk or negedge reset) begin
pirority_req = priority;

if (reset) begin
    grant0 <= 1'b0;
    grant1 <= 1'b0;
    grant2 <= 1'b0;
    grant3 <= 1'b0;
   end
else
begin
    if(priority == 1)
        if (priority req == 2b'00)
            begin
            x=1;
            grant0 <= (grant0*(~x))+(grant1*x);     
            x=0;
            grant0 <= (grant0*(~x))+(grant1*x);
            grant1 <= grant2;
            grant2 <= grant3;
            grant3 <= grant1;
            //  counter 0012300123
            end
        else if (priority req == 2b'01)
            begin
            grant0 <= grant1;
            x=1;
            grant1 <= (grant1*(~x))+(grant2*x);
            x=0;
            grant1 <= (grant1*(~x))+(grant2*x);
            grant2 <= grant3;
            grant3 <= grant1;
            //  counter 0112301123
            end
        else if (priority req == 2b'10)
            begin
            grant0 <= grant1;
            grant1 <= grant2;
            x=1;
            grant2 <= (grant2*(~x))+(grant3*x);
            x=0;
            grant2 <= (grant2*(~x))+(grant3*x);
            grant3 <= grant1;
            //  counter 0122301223
            end
        else if (priority req == 2b'11)
            begin
            grant0 <= grant1;
            grant1 <= grant2;
            grant2 <= grant3;
            x=1;
            grant3 <= (grant3*(~x))+(grant1*x);
            x=0;
            grant3 <= (grant3*(~x))+(grant1*x);
            //  counter 0123301233
            end
    end

    else 
    begin
        grant0 <= ~grant2 * grant3;
        grant1 <= grant0;
        grant2 <= grant1;
        grant3 <= grant2;
        //counter 01230123
    end
end
end

end

endmodule

如您所见，我正在尝试制作循环计数器。每个案例都像 (grant)01230123.., 0012300123.., 0112301123.., 0122301223.., 0123301233...

** Error: (vlog-13069) C:/Modeltech_pe_edu_10.4a/examples/rr_arbiter.v(17): near "always": syntax error, unexpected always, expecting ';' or ','.

** Error: (vlog-13069) C:/Modeltech_pe_edu_10.4a/examples/rr_arbiter.v(22): near "<=": syntax error, unexpected <=.

** Error: C:/Modeltech_pe_edu_10.4a/examples/rr_arbiter.v(22): (vlog-13205) Syntax error found in the scope following 'grant0'. Is there a missing '::'?

Answer 1

第 17 行的错误消息不言自明。它期待一个';'。你错过了一个';'在第 15 行。

如果错误消息看起来毫无意义，请始终向上看屏幕，看看问题是否出在前一行。

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