使用 write-through/write-back 架构时计算有效 CPI
Calculating Effective CPI when using write-through/write-back architecture
所以我试图理解老师给出的作业问题，老实说我迷路了 - 我理解 write-through/write-back 等的概念，但我无法弄清楚所需的实际计算对于有效 CPI，谁能帮帮我？ （问题如下：
The following table provides the statistics of a cache for a
particular program. It is known that the base CPI (without cache
misses) is 1. It is also known that the memory bus bandwidth (the
bandwidth to transfer data between cache and memory) is 4 bytes per
cycle, and it takes one cycle to send the address before data
transfer. The memory spends 10 cycles to store data from bus or fetch
data to bus. The clock rate used by memory and the bus is a quarter of
the CPU clock rate.
Data reads per 1000 instructions: 100
Data writes per 1000 instructions: 150
Instruction cache miss rate: 0.4%
Data cache miss rate: 3%
Block size in bytes: 32
有效 CPI 是基础 CPU 加上缓存未命中的 CPI 贡献。
缓存未命中 CPI 是指令缓存 CPI 和数据缓存 CPI 之和。
缓存未命中成本是读取或写入内存的成本，因此我们需要它。
总线周期的成本是 1（地址）加上 10（内存繁忙时间）+ 8（32 字节块大小除以 4 bytes/cycle）= 19 个周期。将其乘以 4 得到 CPU 个周期。总共是 76 CPU 个周期。
因此 I 缓存未命中的成本是 .004 * 76 = .304 个周期。
D 缓存未命中的成本是 (.10 + .15) * .03 * 76 = .57 个周期
因此有效 CPI 为 1 + .304 + .57 = 1.874 个周期。
所以我试图理解老师给出的作业问题，老实说我迷路了 - 我理解 write-through/write-back 等的概念，但我无法弄清楚所需的实际计算对于有效 CPI，谁能帮帮我？ （问题如下：
The following table provides the statistics of a cache for a particular program. It is known that the base CPI (without cache misses) is 1. It is also known that the memory bus bandwidth (the bandwidth to transfer data between cache and memory) is 4 bytes per cycle, and it takes one cycle to send the address before data transfer. The memory spends 10 cycles to store data from bus or fetch data to bus. The clock rate used by memory and the bus is a quarter of the CPU clock rate.
Data reads per 1000 instructions: 100
Data writes per 1000 instructions: 150
Instruction cache miss rate: 0.4%
Data cache miss rate: 3%
Block size in bytes: 32
有效 CPI 是基础 CPU 加上缓存未命中的 CPI 贡献。
缓存未命中 CPI 是指令缓存 CPI 和数据缓存 CPI 之和。
缓存未命中成本是读取或写入内存的成本，因此我们需要它。
总线周期的成本是 1（地址）加上 10（内存繁忙时间）+ 8（32 字节块大小除以 4 bytes/cycle）= 19 个周期。将其乘以 4 得到 CPU 个周期。总共是 76 CPU 个周期。
因此 I 缓存未命中的成本是 .004 * 76 = .304 个周期。
D 缓存未命中的成本是 (.10 + .15) * .03 * 76 = .57 个周期
因此有效 CPI 为 1 + .304 + .57 = 1.874 个周期。