VHDL 2008 无法驱动具有外部名称别名的信号
VHDL 2008 can't drive a signal with an alias of an external name
请看下面的代码,特别是末尾的 3 行注释。我用 Questasim 10.6c 模拟了这个:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity alias_extname_driving_signal is
port(
clk : in std_logic
);
end alias_extname_driving_signal;
architecture primary of alias_extname_driving_signal is
signal buried_control_vector16 : std_logic_vector(15 downto 0) := (others => '0');
begin
buried_control_vector16 <= std_logic_vector(unsigned(buried_control_vector16) + 1) when rising_edge(clk);
end architecture primary;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity alias_extname_driving_signal_tb is
end alias_extname_driving_signal_tb;
architecture primary of alias_extname_driving_signal_tb is
signal clk : std_logic := '0';
signal control_vector16 : std_logic_vector(15 downto 0) := (others => '0');
alias control_vector16_alias is control_vector16;
alias buried_control_vector16_alias is << signal .alias_extname_driving_signal_tb.uut.buried_control_vector16 : std_logic_vector(15 downto 0) >>;
signal vector16 : std_logic_vector(15 downto 0);
begin
clk <= not clk after 10 ns;
control_vector16 <= std_logic_vector(unsigned(control_vector16) + 1) when rising_edge(clk);
uut : entity work.alias_extname_driving_signal
port map(
clk => clk
);
-- vector16 <= << signal .alias_extname_driving_signal_tb.uut.buried_control_vector16 : std_logic_vector(15 downto 0) >>; -- this statement works
-- vector16 <= control_vector16_alias; -- this statement works
-- vector16 <= buried_control_vector16_alias; -- vector16 remains perpetually undefined with this statement
end architecture primary;
如您所见,我可以驱动具有外部名称的信号,即本地信号的别名,但不能驱动外部名称的别名。有什么方法可以使用外部名称的别名来驱动 vhdl-2008 中的信号?
在此先感谢您的帮助。
外部名称只能在详细说明所引用的对象之后声明。
VHDL 从测试台开始阐述。首先阐述了声明区域。然后按顺序详细说明代码区域。如果它找到一个组件,它会详细说明它和任何子组件。当它完成对组件(和任何子组件)的详细说明时,它会在它停止的地方继续详细说明测试台。
因此,您需要将别名声明移动到块语句或进程中。块语句的代码如下。请注意带有块语句的标签是必需的。
architecture primary of alias_extname_driving_signal_tb is
signal clk : std_logic := '0';
signal control_vector16 : std_logic_vector(15 downto 0) := (others => '0');
alias control_vector16_alias is control_vector16;
signal vector16 : std_logic_vector(15 downto 0);
begin
clk <= not clk after 10 ns;
control_vector16 <= std_logic_vector(unsigned(control_vector16) + 1) when rising_edge(clk);
uut : entity work.alias_extname_driving_signal
port map(
clk => clk
);
myblock : block
alias buried_control_vector16_alias is << signal .alias_extname_driving_signal_tb.uut.buried_control_vector16 : std_logic_vector(15 downto 0) >>;
begin
vector16 <= << signal .alias_extname_driving_signal_tb.uut.buried_control_vector16 : std_logic_vector(15 downto 0) >>; -- this statement works
vector16 <= control_vector16_alias; -- this statement works
vector16 <= buried_control_vector16_alias; -- vector16 remains perpetually undefined with this statement
end block myblock ;
end architecture primary;
请看下面的代码,特别是末尾的 3 行注释。我用 Questasim 10.6c 模拟了这个:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity alias_extname_driving_signal is
port(
clk : in std_logic
);
end alias_extname_driving_signal;
architecture primary of alias_extname_driving_signal is
signal buried_control_vector16 : std_logic_vector(15 downto 0) := (others => '0');
begin
buried_control_vector16 <= std_logic_vector(unsigned(buried_control_vector16) + 1) when rising_edge(clk);
end architecture primary;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity alias_extname_driving_signal_tb is
end alias_extname_driving_signal_tb;
architecture primary of alias_extname_driving_signal_tb is
signal clk : std_logic := '0';
signal control_vector16 : std_logic_vector(15 downto 0) := (others => '0');
alias control_vector16_alias is control_vector16;
alias buried_control_vector16_alias is << signal .alias_extname_driving_signal_tb.uut.buried_control_vector16 : std_logic_vector(15 downto 0) >>;
signal vector16 : std_logic_vector(15 downto 0);
begin
clk <= not clk after 10 ns;
control_vector16 <= std_logic_vector(unsigned(control_vector16) + 1) when rising_edge(clk);
uut : entity work.alias_extname_driving_signal
port map(
clk => clk
);
-- vector16 <= << signal .alias_extname_driving_signal_tb.uut.buried_control_vector16 : std_logic_vector(15 downto 0) >>; -- this statement works
-- vector16 <= control_vector16_alias; -- this statement works
-- vector16 <= buried_control_vector16_alias; -- vector16 remains perpetually undefined with this statement
end architecture primary;
如您所见,我可以驱动具有外部名称的信号,即本地信号的别名,但不能驱动外部名称的别名。有什么方法可以使用外部名称的别名来驱动 vhdl-2008 中的信号?
在此先感谢您的帮助。
外部名称只能在详细说明所引用的对象之后声明。
VHDL 从测试台开始阐述。首先阐述了声明区域。然后按顺序详细说明代码区域。如果它找到一个组件,它会详细说明它和任何子组件。当它完成对组件(和任何子组件)的详细说明时,它会在它停止的地方继续详细说明测试台。
因此,您需要将别名声明移动到块语句或进程中。块语句的代码如下。请注意带有块语句的标签是必需的。
architecture primary of alias_extname_driving_signal_tb is
signal clk : std_logic := '0';
signal control_vector16 : std_logic_vector(15 downto 0) := (others => '0');
alias control_vector16_alias is control_vector16;
signal vector16 : std_logic_vector(15 downto 0);
begin
clk <= not clk after 10 ns;
control_vector16 <= std_logic_vector(unsigned(control_vector16) + 1) when rising_edge(clk);
uut : entity work.alias_extname_driving_signal
port map(
clk => clk
);
myblock : block
alias buried_control_vector16_alias is << signal .alias_extname_driving_signal_tb.uut.buried_control_vector16 : std_logic_vector(15 downto 0) >>;
begin
vector16 <= << signal .alias_extname_driving_signal_tb.uut.buried_control_vector16 : std_logic_vector(15 downto 0) >>; -- this statement works
vector16 <= control_vector16_alias; -- this statement works
vector16 <= buried_control_vector16_alias; -- vector16 remains perpetually undefined with this statement
end block myblock ;
end architecture primary;