可以从 EL0 刷新 arm64 缓存吗？
Can arm64 cache be flushed from EL0?
我正在阅读一篇学术论文，其中指出 "The ARM architecture also includes instructions to evict cache lines. However, these instructions can only be used when the processor is in an elevated privilege mode."
这是真的吗？我一直在搜索 ARM 文档，但没有看到任何表明我不能从 "ARM Cortex-A Series Programmer’s Guide for ARMv8-A" 第 11.5 章 http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.den0024a/BABJDBHI.html
下的 EL0 执行此操作的内容
这是可配置的。
来自 ARMv8 Architecture Reference Manual，第 D3-1988 页：
EL0 accessibility to cache maintenance instructions
The SCTLR_EL1.UCI bit enables EL0 access for the DC CVAU, DC CVAC, DC CVAP, DC CIVAC, and IC IVAU instructions. When EL0 use of these instructions is disabled because SCTLR_EL1.UCI == 0, executing one of these instructions at EL0 generates a trap to EL1, that is reported using EC = 0x18.
For these instructions read access permission is required. When the value of SCTLR_EL1.UCI is 1:
- For the
DC CVAU, DC CVAC, DC CVAP, and DC CIVAC instructions, if the instruction is executed at EL0 and the address specified in the argument cannot be read at EL0, a Permission fault is generated.
- For the
IC IVAU instruction, if the instruction is executed at EL0 and the address specified in the argument cannot be read at EL0, it is IMPLEMENTATION DEFINED whether a Permission fault is generated.
Software can read the CTR_EL0 to discover the stride needed for cache maintenance instructions. The SCTLR_EL1.UCT bit enables EL0 access to the CTR_EL0. When EL0 access to the Cache Type register is disabled, a register access instruction executed at EL0 is trapped to EL1 using EC = 0x18.
这篇论文确实是正确的。如果您通读了 ARMV8 参考手册的 C5.3 部分（在此处找到 https://static.docs.arm.com/ddi0487/ca/DDI0487C_a_armv8_arm.pdf），您会发现缓存维护指令始终可以在异常级别 EL1 到 EL3 中访问。
用户 space 程序 运行 在 EL0 中，而内核在 EL1 或 EL2 中（EL2 用于管理程序），EL3 用于安全监视器代码。可以从 EL0 访问一些缓存维护指令，但可以根据确切的指令将其禁用或捕获。
我正在阅读一篇学术论文，其中指出 "The ARM architecture also includes instructions to evict cache lines. However, these instructions can only be used when the processor is in an elevated privilege mode."
这是真的吗？我一直在搜索 ARM 文档，但没有看到任何表明我不能从 "ARM Cortex-A Series Programmer’s Guide for ARMv8-A" 第 11.5 章 http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.den0024a/BABJDBHI.html
下的 EL0 执行此操作的内容这是可配置的。
来自 ARMv8 Architecture Reference Manual，第 D3-1988 页：
EL0 accessibility to cache maintenance instructions
The
SCTLR_EL1.UCIbit enables EL0 access for theDC CVAU,DC CVAC,DC CVAP,DC CIVAC, andIC IVAUinstructions. When EL0 use of these instructions is disabled becauseSCTLR_EL1.UCI == 0, executing one of these instructions at EL0 generates a trap to EL1, that is reported using EC =0x18.For these instructions read access permission is required. When the value of
SCTLR_EL1.UCIis 1:
- For the
DC CVAU,DC CVAC,DC CVAP, andDC CIVACinstructions, if the instruction is executed at EL0 and the address specified in the argument cannot be read at EL0, a Permission fault is generated.- For the
IC IVAUinstruction, if the instruction is executed at EL0 and the address specified in the argument cannot be read at EL0, it isIMPLEMENTATION DEFINEDwhether a Permission fault is generated.Software can read the
CTR_EL0to discover the stride needed for cache maintenance instructions. TheSCTLR_EL1.UCTbit enables EL0 access to theCTR_EL0. When EL0 access to the Cache Type register is disabled, a register access instruction executed at EL0 is trapped to EL1 using EC =0x18.
这篇论文确实是正确的。如果您通读了 ARMV8 参考手册的 C5.3 部分（在此处找到 https://static.docs.arm.com/ddi0487/ca/DDI0487C_a_armv8_arm.pdf），您会发现缓存维护指令始终可以在异常级别 EL1 到 EL3 中访问。
用户 space 程序 运行 在 EL0 中，而内核在 EL1 或 EL2 中（EL2 用于管理程序），EL3 用于安全监视器代码。可以从 EL0 访问一些缓存维护指令，但可以根据确切的指令将其禁用或捕获。