如何将不断变化的 STD_LOGIC 输出中的位分配给 STD_LOGIC_VECTOR 输入

Question

我是这个网站的新手，我有一个问题希望得到帮助。我正在为由发射器和接收器组成的 LFSR 编写 VHDL 代码。发射器应该生成一个随机二进制数（前导码，它确实如此）然后必须连接这个二进制数，但我首先需要将它放在 STD_LOGIC_VECTOR 中，这就是我遇到的问题。

这是我的测试台代码，必须在其中进行此分配，在此先感谢您的帮助：

library ieee;
use ieee.std_logic_1164.all; 

entity testbench is --definig the entity
end testbench;

architecture tb1 of testbench is

    component transmitter is port(
        clk :in std_logic;
        reset:in std_logic;
        enable:in std_logic;
        output :out std_logic);--output is the random generated binary which i need to pass to a vector
    end component;

    --type bit_vector is array (natural range <>) of bit; --this is so that we can define the whole thing otherwise bit can
    --only be 1 or 0 this allows to define them as vectors

    constant SOF: std_logic_vector(0 to 15) := "0101010100001010";  
    constant trailer: std_logic_vector(0 to 7) := "10111110";
    constant payload: std_logic_vector(0 to 7) := "01110010";
    constant L: std_logic_vector(0 to 7) := "00101110";
    signal preamble: std_logic_vector(0 to 95);

    signal clk , reset, enable : std_logic;--output signal
    signal data_packet: std_logic_vector(0 to 135);
    signal output: std_logic;

begin


    --problem is here
    --my attempt
    get_preamble: process
        variable i: std_logic;--this will be used to walk through the preamble vector and put the out put values in 
        --variable j: std_logic;
    begin

        n1: for i in 0 to 95 loop
            if output = '1' then
                preamble(i) <= '1';
            end if;
        end loop;

        if output = '0' then
            for i in 0 to 95 loop
                preamble(i) <= '0';
            end loop;
        end if;

        wait;
    end process;--end of get_preamble

    concatenation :process 
    begin
        data_packet <= preamble & SOF & L & payload & trailer;
        wait;
    end process;
END tb1;

Answer 1

您是否正在寻找这样的东西？它将从 "output" 中获取 96 位的流并将它们放入 "preamble" 中。然后将前导码连接到数据包。

for i in 0 to 95 loop
   wait until rising_edge(clk);
   preamble(i) <= output;
end loop;

data_packet <= preamble & SOF & L & payload & trailer;

Answer 2

根据您的问题，您是说您正在尝试将值 output 与 preamble 向量的其余部分连接起来。你应该改变这个：

n1: for i in 0 to 95 loop

if output = '1' then
   preamble(i) <= '1';
end if;
     end loop;
if output = '0' then

   for i in 0 to 95 loop

   preamble(i) <= '0';
end loop;
   end if;

对此：

n1: for i in 0 to 95 loop
  wait until clk'EVENT and clk = '1';
  preamble(i) <= output
end loop;

因为你有一个时钟，当你的时钟有一个上升沿时，尝试获取每个值。不需要每次都检查值，直接添加到vector中即可。

编辑： 你应该在另一个进程中等待同样的事情，或者等待 preamble 完成加载它的 96 个值，这取决于你想要完成。

如何将不断变化的 STD_LOGIC 输出中的位分配给 STD_LOGIC_VECTOR 输入

How to assign bits from a changing STD_LOGIC output to a STD_LOGIC_VECTOR input

vhdl