在 Verilog 中用快时钟和慢时钟生成脉冲

Question

我正在用 Verilog 编写程序。我在实现每次都会在慢速时钟的上升沿出现并在快速时钟的上升沿消失的短脉冲时遇到问题。

下面贴上我写的代码，给我这样一个脉冲，可惜只在第一个边上出现过一次，再也没有出现过。

reg cnt_write_bit1, cnt_write_bit2; 
initial cnt_write_bit1 = 0;
initial cnt_write_bit2 = 0;
reg cnt_write_fifo;
initial cnt_write_fifo = 0; 

always @ (posedge clk_1kHz)
begin : WRITE_FIFO
    if (cnt_write_fifo)
    begin
        cnt_write_bit1 <= 0;
    end
    else
    begin
        cnt_write_bit1 <= 1;
    end
end

always @ (posedge clk_50MHz)
begin : STOP_WRITE_FIFO
    if (cnt_write_fifo)
    begin
        cnt_write_bit2 <= 0;
    end
    else //if (!cnt_write_bit1)
    begin
        cnt_write_bit2 <= 1;
    end
end

always @ (cnt_write_bit1, cnt_write_bit2)
begin 
    if (cnt_write_bit1 && cnt_write_bit2)
    begin 
        cnt_write_fifo <= 1;
    end
    else if (!cnt_write_bit2)
    begin
        cnt_write_fifo <= 0;
    end
end

在模拟中它看起来像这样：

"cnt_write_fifo" 信号上的脉冲在慢时钟的每个上升沿上应该是可重复的，但不幸的是它不是。

如有任何帮助，我将不胜感激。

Answer 1

如果像你说的时钟是 a-synchronous 你不能做你想做的事。
假设在某个时间点，两个时钟上升沿相隔 1ps，（慢速时钟领先）然后您需要生成一个高 1ps 的信号。除了实现它的困难之外，你会用它做什么？

我建议您将 'specification' 更改为：

"There is a signal generated from a slow clock. If there is a rising edge I want to have a pulse of 1 clock cycle long on a non-related faster clock. There is allowed a maximum of X fast clock pulses delay between the signal changing on the slow clock generating a pulse on the fast clock (X>=2)".

抱歉，主要编辑：我的大脑没有打开！
使用同步将信号从慢时钟传输到快时钟。然后在快时钟域中找到上升沿：

//
// Transfer a signal from a slow clock to a fast clock
// Also detect the rising edge in the fast clock domain
//
module signal_transfer 
(

  input      slow_clock, 
  input      slow_signal,

  input      reset_n,     // reset for fast clock domain
  input      fast_clock,
  output reg fast_signal,
  output     fast_rising
  );

reg signal_meta,signal_delay;


   always @(posedge fast_clock or negedge reset_n)
   begin
      if (!reset_n)
      begin
         signal_meta  <= 1'b0;
         fast_signal  <= 1'b0;
         signal_delay <= 1'b0;
      end
      else
      begin
         signal_meta  <= slow_signal;
         fast_signal  <= signal_meta;
         signal_delay <= fast_signal;
      end
   end

   assign fast_rising = fast_signal & !signal_delay;

endmodule

在 Verilog 中用快时钟和慢时钟生成脉冲

Generating a pulse with fast and slow clock in Verilog

signals

verilog

fpga

clock

pulse