如何检查使用运算符重载添加 std_logic_vector 时生成的任何进位？

Question

我正在尝试使用下面给出的符号添加两个 std_logic_vectors：-

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--use IEEE.NUMERIC_STD.ALL;

entity adder is
port( a:in std_logic_vector(31 downto 0);
    b:in std_logic_vector(31 downto 0);
    o:out std_logic_vector(31 downto 0));
end adder;

architecture Behavioral of adder is

begin
o<=a+b;

end Behavioral;

Answer 1

一种可能是生成带进位的结果，然后拆分，如：

architecture Behavioral of adder is
    signal c_o : std_logic_vector(o'length downto 0);  -- Result with carry
    signal c   : std_logic;  -- Carry only
begin
    c_o <= ('0' & a) + b;  -- Result with carry; extended with '0' to keep carry 
    o <= c_o(o'range);     -- Result without carry
    c <= c_o(c_o'left);    -- Carry only
end Behavioral;

Answer 2

你可以做到。进位未保存，但据报告存在溢出。

function "+" (Add1: std_logic_vector; Add2: std_logic_vector) return std_logic_vector is
    variable big_sum: bit_vector(Add1'LENGTH downto 0);
begin
    big_sum = Add1 + Add2;
    assert big_sum(Add1'LENGTH) = 0
      report "overflow"
      severity warning;
    return big_sum(Add1'LENGTH-1 downto 0);

当然，您需要定义一个新包并将该包包含在您现有的文件中。

Answer 3

o<=std_logic_vector(unsigned(a)+unsigned(b))

尽管我建议您在您的端口上使用 unsigned/signed（并且有一个延迟的时钟周期）。

如果你想要进位

o_with_carry <= std_logic_vector('0'&unsigned(a)+unsigned(b));
o_carry <= o_with_carry(o_with_carry'high);
o <=  o_with_carry(o'range);

如何检查使用运算符重载添加 std_logic_vector 时生成的任何进位？

how to check for any carry generated while adding std_logic_vector using operator overloading?

vhdl