错误 "type of identifier does not agree with its usage as "“类型”在 VHDL 中的确切含义是什么？端口映射会影响'type'吗？

Question

我在使用 VHDL 解决错误“标识符类型与其用法不一致”时遇到了问题。据我了解，这意味着赋值时出现了错误。例如，将 std_logic 分配给 std_logic_vector 或者可能将 std_logic 分配给某个位。正确吗？

我在尝试执行错误发生的端口 mapping.Here 后收到错误：

LIBRARY ieee; 
USE ieee.std_logic_1164.all; 
USE ieee.std_logic_1164.all; 
USE  IEEE.STD_LOGIC_ARITH.all;
USE  IEEE.STD_LOGIC_UNSIGNED.all;        
ENTITY ALU1 IS
 PORT (a,b,ainverse,binverse, cin:IN std_logic;
    operation: IN std_logic;
        cout, result,resolution : OUT std_logic
   );
 END ALU1;


ARCHITECTURE archAl OF ALU1 IS

COMPONENT adder
    PORT(a,b, cin: IN std_logic;
            cout,resolution: OUT std_logic);
END COMPONENT;

COMPONENT AND1
    PORT(a, b :IN std_logic;
        resolution: OUT std_logic);
END COMPONENT;

COMPONENT OR1
    PORT(a, b : IN std_logic;
        resolution: OUT std_logic);
END COMPONENT;

COMPONENT mux2
 PORT( a, inverse : IN std_logic;
            resolution  :   OUT std_logic
 );
END COMPONENT;

COMPONENT XOR1
 PORT(a,b : IN std_logic;
     resolution : OUT std_logic
     );
END COMPONENT;

 --SIGNAL resolution: std_logic;



BEGIN --ARCHITECTURE BEGIN
andA:  mux2 PORT MAP(a, ainverse, resolution);
andB:  mux2 PORT MAP(b, binverse, resolution);
 resolutionAnd: AND1 PORT MAP (andA, andB, resolution);
  addA: mux2 PORT MAP(a, ainverse, resolution);
addB: mux2 PORT MAP(b, binverse, resolution);
    resolutionOr: OR1 PORT MAP (a, b, resolution);

    resolutionAdd: adder PORT MAP(ainverse, binverse, cin, cout, resolution);

resolutionXor: XOR1 PORT MAP (a,b, resolution);
PROCESS(operation, a, ainverse, resolution, b, cin,cout, BINVERSE) is
BEGIN --PROCESS BEGIN
 IF operation = "00" THEN
    result<=resolutionAnd;
 ELSIF operation = "01" THEN

    result<=resolutionOr;
 ELSIF operation = "10" THEN

     result<=resolutionAdd;

ELSIF operation ="11" THEN

     result<=resolutionAXor;
 END IF;

END PROCESS;
END archAl;

错误发生在resolutionAnd: AND1 PORT MAP (andA, andB, resolution);

我得到 Error (10476): VHDL error at alu.vhd(158): type of identifier "andA" does not agree with its usage as "std_logic" type 和 Error (10476): VHDL error at alu.vhd(158): type of identifier "andB" does not agree with its usage as "std_logic" type。因此，合乎逻辑的做法是搜索影响 andA 和 B 的 mux2，以查看分配的类型之间是否存在不一致。

mux2 的代码是：

ENTITY mux2 IS
PORT(a, inverse: IN std_logic;
   resolution       :   OUT std_logic);
END mux2;

ARCHITECTURE archMux2 OF mux2 IS
  BEGIN
     PROCESS(a, inverse)
     BEGIN
         IF inverse = '0' THEN
            resolution <= a;
         ELSE
            resolution <= NOT a;
        END IF;
     END PROCESS;
 END archMux2;

我无法检测到分配的类型有任何不一致之处。所以我想我没有正确理解错误或者发生了错误但我不知道。有人可以帮忙吗？

Answer 1

andA 和 andB 是标签：

andA:  mux2 PORT MAP(a, ainverse, resolution);
andB:  mux2 PORT MAP(b, binverse, resolution);
^^^^

您似乎已将它们连接到 AND 组件的端口 resolutionAnd:

resolutionAnd: AND1 PORT MAP (andA, andB, resolution);
                              ^^^^  ^^^^

错误 "type of identifier does not agree with its usage as "“类型”在 VHDL 中的确切含义是什么？端口映射会影响'type'吗？

What does the error "type of identifier does not agree with its usage as " " type" mean exactly in VHDL? Does port mapping affect the 'type'?

fpga

vhdl

intel-fpga

quartus