使用 VHDL 对信号进行卷积

Question

我一直致力于在 MultiSim Student PE Edition 中使用 VHDL 实现卷积运算。以下代码编译成功，但是当我单击“模拟”时出现以下错误：

# vsim 
# Start time: 10:32:20 on Apr 26,2015
# Loading std.standard
# ** Error: (vsim-13) Recompile work.convolution because work.convolution has changed.
# 
# ** Error (suppressible): (vsim-12) Recompile work.convolution(behavioral) after work.convolution, work.convolution are recompiled.
# 
# Error loading design

这里是源代码：

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_arith.all;

package Convolution IS
    TYPE real_vector is ARRAY(integer RANGE <>) OF real;
end;

use work.Convolution.ALL;

entity convolution is
    port (x:in real_vector(0 to 3);
          h:in real_vector(0 to 1);
          y:out real_vector (0 to 4));
end convolution;



architecture Behavioral of convolution is
BEGIN   
    process (x,h)
    variable sum :real := 0.0;
    variable temp :integer := 0;

    begin
    for k in y'range loop
        sum:=0.0;
        for n in h'range loop
                temp := k-n;
            if temp >= 0 then
                sum := sum + h(n)*x(temp);  --we are assuming all singnals are positively indexed, negative indices deafult to 0.       
            end if;
            end loop;
            y(k) <= sum ;
    end loop;
    end process;
end Behavioral;

请帮我解决这个问题。

Answer 1

你有一个名字冲突。您在同一个（工作）库中有两个同名的主要单元。

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- use IEEE.std_logic_arith.all;

package Convolution_pkg IS
    TYPE real_vector is ARRAY(integer RANGE <>) OF real;
end;

use work.Convolution_pkg.ALL;

...

更改一个或另一个的名称。（这显示更改包名称）。

您也可以将卷积包分析到不同的（例如它自己的）库中。

在同一个图书馆的两个主要单元中使用相同的名称有点麻烦 22。

参见 IEEE Std 1076-2008，13.5 分析顺序第 5 段：

A given library unit is potentially affected by a change in any library unit whose name is referenced within the given library unit. A secondary unit is potentially affected by a change in its corresponding primary unit. If a library unit is changed (e.g., by reanalysis of the corresponding design unit), then all library units that are potentially affected by such a change become obsolete and shall be reanalyzed before they can be used again.

使用 VHDL 对信号进行卷积

Convolution of signals using VHDL

signals

signal-processing

vhdl

modelsim