vhdl代码理解，是否存在关于可能无限循环的modelsim错误

Question

--
-- VHDL Architecture di_lib.ShiftRegister1.ShiftRegister1
--
-- Created:
--          by - 294162.UNKNOWN (VD1210)
--          at - 14:19:36 10-04-2015
--
-- using Mentor Graphics HDL Designer(TM) 2010.2a (Build 7)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;

LIBRARY WORK;
USE WORK.CALC_PKG.ALL;
LIBRARY di_lib;
USE di_lib.calc_pkg.all;
USE ieee.NUMERIC_STD.all;

ENTITY ShiftRegister1 IS
   PORT( 
      d_out       : OUT    Std_Logic_Vector (7 DOWNTO 0);
      multiplexer : IN     Std_Logic_Vector (7 DOWNTO 0);
      carry       : IN     std_logic;
      load_out    : IN     std_logic;
      f_code      : IN     std_logic_vector (2 DOWNTO 0);
      out_loaded  : OUT    std_logic
   );

-- Declarations

END ShiftRegister1 ;

--
ARCHITECTURE ShiftRegister1 OF ShiftRegister1 IS
BEGIN

  ShiftRegister1 : process

  variable remember, multiplexer_var       : std_logic_vector(7 DOWNTO 0);
  variable state          : std_logic_vector(2 DOWNTO 0);
  variable counter        : integer := 0; 
        begin

          state := f_code;

        case state is

        when "000" => 
            d_out <= multiplexer;

        when "001" =>
            d_out <= multiplexer;

        when "010" =>
                multiplexer_var := multiplexer;
            if load_out = '1' then 
              if carry = '1' then
                --shifting is done without function SRL
                remember(0) := multiplexer_var(1);
                remember(1) := multiplexer_var(2);
                remember(2) := multiplexer_var(3);
                remember(3) := multiplexer_var(4);
                remember(4) := multiplexer_var(5);
                remember(5) := multiplexer_var(6);
                remember(6) := multiplexer_var(7);
                remember(7) := '1';
                d_out <= remember;
                out_loaded <= '1';

              elsif  carry = '0' then
                remember(0) := multiplexer_var(1);
                remember(1) := multiplexer_var(2);
                remember(2) := multiplexer_var(3);
                remember(3) := multiplexer_var(4);
                remember(4) := multiplexer_var(5);
                remember(5) := multiplexer_var(6);
                remember(6) := multiplexer_var(7);
                remember(7) := '0';
                d_out <= remember;
                out_loaded <= '1';
              end if;
            end if;

        when "011" =>
            if load_out = '1' then
              d_out <= multiplexer;
              out_loaded <= '1';
            end if;

        when others => null;

        end case;
   end process;

END ARCHITECTURE ShiftRegister1;

--给出的错误--

-- Compiling architecture shiftregister1 of shiftregister1
**Warning: [2] <...>vhd(109): (vcom-1090) Possible infinite loop: Process contains no WAIT statement.
Warning: Cannot create unmappedlibrary work

问题：在此代码中可能会发生无限循环的地方？

Answer 1

在 VHDL 中，进程的执行时间是瞬时的。此外，进程在完成后立即重新执行。因此你的过程形成了一个无限循环。

要解决此问题，请添加 wait 语句或使用敏感度列表。具有敏感列表的进程只会在敏感列表信号之一发生变化时执行。类似于：

process(load_out, carry, multiplexer, f_code)

您必须确保将过程使用的所有信号添加到敏感度列表中，否则您将得到模拟不匹配，因为敏感度列表在综合时被忽略。

vhdl代码理解，是否存在关于可能无限循环的modelsim错误

vhdl code understanding, if there is modelsim error about possible infinite loop

vhdl