fpga不能得到简单的寄存器输出

Question

我知道这是基本的，但我很难让它发挥作用。我来自 IO 引脚 "reading"，我想要 'save' 简单缓冲区中的位。出于某种原因，我在输出中没有得到任何东西。这是我运行和 lattice 的网表分析器的代码，以及我通过运行测试台获得的波形。我尝试应用我在其他代码中看到的内容，但它没有用。

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity InputBuffer is
    generic( n: natural := 4 );
    Port (    
        clk    : in STD_LOGIC;
        CLK65  : IN STD_LOGIC;
        En     : in STD_LOGIC;
        STRT   : OUT STD_LOGIC;
        Ipin   : in  STD_LOGIC_VECTOR (n-1 downto 0);
        Output : out  STD_LOGIC_VECTOR (n-1 downto 0)
        );
end InputBuffer;

architecture Behavioral of InputBuffer is
    signal temp : STD_LOGIC_VECTOR(n-1 downto 0);
    SIGNAL CLK2 : STD_LOGIC;
begin
    -- invert the signal from the push button switch and route it to the LED
    process(clk, En)
    begin
        if( En = '1') then
            temp <= B"0000";
        elsif rising_edge(clk) then
            temp <= Ipin; 
        end if;
    end process;
    Output <=  temp;
    STRT <= CLK65;
end Behavioral;

这是我正在使用的测试平台。

     -- VHDL Test Bench Created from source file InputBuffer.vhd -- Fri Jun 29 22:45:57 2018

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

ENTITY testbench IS
END testbench;

ARCHITECTURE behavior OF testbench IS 

    COMPONENT InputBuffer
    PORT(
        clk : IN std_logic;
        CLK65 : IN std_logic;
        En : IN std_logic;
        Ipin : IN std_logic_vector(3 downto 0);          
        STRT : OUT std_logic;
        Output : OUT std_logic_vector(3 downto 0)
        );
    END COMPONENT;

    SIGNAL clk :  std_logic;
    SIGNAL CLK65 :  std_logic;
    SIGNAL En :  std_logic;
    SIGNAL STRT :  std_logic;
    SIGNAL Ipin :  std_logic_vector(3 downto 0);
    SIGNAL Output :  std_logic_vector(3 downto 0);  

    constant delay : time := 10 ns;

BEGIN

-- Please check and add your generic clause manually
    uut: InputBuffer PORT MAP(
        clk => clk,
        CLK65 => CLK65,
        En => En,
        STRT => STRT,
        Ipin => Ipin,
        Output => Output
    );

    En <= '0';
    clk <= '0';
    clk65 <= '0';
    Ipin <= B"0000";
-- *** Test Bench - User Defined Section ***
   tb : PROCESS
   BEGIN  
      wait for delay;
      clk <='1'; 
      clk65 <='1';
      wait for delay;
      clk <='0';


      wait for delay;
      clk <='1';
      clk65 <='0';

      wait for delay;
      clk <='0';
      --wait; -- will wait forever
   END PROCESS;
-- *** End Test Bench - User Defined Section ***

END;

Answer 1

将您的测试平台添加到您的问题中提供了 Minimal, Complete and Verifiable example。

对于我们这些无法准确解释您的波形显示的人，彩色版本以及显示移动到波形关键部分的值的光标可能会有所帮助：

在此波形显示中，我们看到标量信号（clk 等）显示为 'X'，在您的 Lattice 工具链中显示为 'X' 的红色矩形（上面的波形是用gtkwave 和 ghdl).

时钟在 'X' 和 '0' 之间变化告诉我们在测试台中有两个 clk 驱动程序，当两个驱动程序都驱动 '0' 时显示 '0'。

驱动程序是通过分配给进程中的信号来创建的。

并发信号分配被细化为等效过程（IEEE Std 1076-2008 11.6 并发信号分配语句 "A concurrent signal assignment statement represents an equivalent process statement that assigns values to signals." 其敏感列表由 10.2 Wait 语句 "This rule is also used to construct the sensitivity sets of the wait statements in the equivalent process statements for concurrent procedure call statements (11.4), concurrent assertion statements (11.5), and concurrent signal assignment statements (11.6)." 确定。

具有多个驱动器的信号值按照 14.7.3.2 驱动值中的规定确定：

e) If S is a basic signal:

...
— If S is a resolved signal and has one or more sources, then the driving values of the sources of S are examined. It is an error if any of these driving values is a composite where one or more subelement values are determined by the null transaction (see 10.5.2.2) and one or more subelement values are not determined by the null transaction. If S is of signal kind register and all the sources of S have values determined by the null transaction, then the driving value of S is unchanged from its previous value. Otherwise, the driving value of S is obtained by executing the resolution function associated with S, where that function is called with an input parameter consisting of the concatenation of the driving values of the sources of S, with the exception of the value of any source of S whose current value is determined by the null transaction.

在 IEEE 包 std_logic_1164 中找到类型 std_logic 的解析函数。

那么clk（和clk64）的两个驱动在哪里？

    En <= '0';
    clk <= '0';
    clk65 <= '0';
    Ipin <= B"0000";
-- *** Test Bench - User Defined Section ***
   tb : PROCESS
   BEGIN  
      wait for delay;
      clk <='1'; 
      clk65 <='1';
      wait for delay;
      clk <='0';


      wait for delay;
      clk <='1';
      clk65 <='0';

      wait for delay;
      clk <='0';
      --wait; -- will wait forever
   END PROCESS;

在进程 tb 的正上方有四个并发赋值语句。可以注释掉导致多个驱动程序的两个（clk 和 clk64），而不需要信号声明中的初始值，因为您在过程中强制它们的值。

如果我们注释掉对 clk 和 clk65 的并发信号分配，则您的测试台可以工作：

fpga不能得到简单的寄存器输出

fpga can't get simple register output

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vhdl

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