PIC18编译错误195是什么意思？
what does the PIC18 compile error 195 mean?
我是 PIC18 编程的新手 micro-controllers，当我尝试编译我的代码时，我总是收到编译错误 195。我使用的 PIC 是 PIC18F46k80，我尝试为其编程的应用程序是针对已经嵌入 PIC 的硬件，所以我无法更改 Pin 配置（我没有设计硬件).我试图让我的 PIC 通过 bit-banging 执行稍微修改的 SPI 协议，因为内部外围设备的正确引脚尚未连接。每当我尝试设置 RA6 或 RA5 时，我都会将 运行 保留在这个编译错误中，即使（我认为）我已经配置了引脚以使其可写（不提供内部时钟）。具体来说，我在尝试设置 LATA6 = x 或 LATA5 = x 时遇到错误。在 MPLAB X 中，我编写 LATA6 或 LATA5 的每一期都被突出显示。有人可以帮我 writing/setting 这些图钉吗？
以下代码的任何实例都会导致问题：
LATA5 = 0;
//or
LAT6 = 0;
//or
LAT6 = 1;
如果需要，我可以发送整个文件，包括 headers 和配置文件 :) 欢迎任何帮助。
完整代码如下：
#include "mcc_generated_files/mcc.h"
#include <stdio.h>
#include<stdlib.h>
#include<xc.h>
//Define words for transfer//
uint8_t FR1IByte = 0x01;
int FR1DBytes = 0x900000;
uint8_t CSRIByte = 0x00;
uint8_t CSRCH0 = 0x10;
uint8_t CSRCH1 = 0x20;
uint8_t CSRCH2 = 0x40;
uint8_t CFTWIByte = 0x04;
uint32_t CFTWCH0 = 0x42680000;
uint32_t CFTWCH1 = 0x1F400000;
uint32_t CFTWCH2 = 0x3E800000;
//Functions to perform SPI//
void SPItransfer8( uint8_t byte)
{
// local variable declaration
int i;
for (i = 0; i <8; i++){ //compares MSB with mask. If it matches, it will transfer a 1//
if(byte & 0x80)
{
LATC5 = 1;
}
else
{
LATC5 = 0;
}
// Pulses clock for transfer of data//
LATA6 = 1;
LATA6 = 0;
// Logical shift left so that next byte can be read//
byte <<= 1;
}
}
void SPItransfer24( int bytes)
{
// local variable declaration
int i;
for (i = 0; i <24; i++);
{ //compares MSB with mask. If it matches, it will transfer a 1//
if(bytes & 0x800000)
{
LATC5 = 1;
}
else
{
LATC5 = 0;
}
// Pulses clock for transfer of data//
LATA6 = 1;
LATA6 = 0;
// Logical shift left so that next byte can be read//
bytes <<= 1;
}
}
void SPItransfer32( uint32_t bytes)
{
// local variable declaration
int i;
for (i = 0; i <32; i++);
{ //compares MSB with mask. If it matches, it will transfer a 1//
if(bytes & 0x80000000)
{
LATC5 = 1;
}
else
{
LATC5 = 0;
}
// Pulses clock for transfer of data//
LATA6 = 1;
LATA6 = 0;
// Logical shift left so that next byte can be read//
bytes <<= 1;
}
}
void main(void)
{
TRISE = 0x03;
TRISA = 0b1001111;
// Initialize the device//
SYSTEM_Initialize();
// Perform master reset on DDS to set the device to its default state (Active high on E2)//
LATE1 = 1;
LATE1 = 0;
// Delay to allow the system to load (PLL takes time to lock) //
__delay_ms(10)
//Set RA5 to low to prevent power down//
LATA5 = 0;
//Set RA6 to low for SPI clock//
LATA6 = 0;
//Transfers the Function Register 1 Information Byte//
SPItransfer8(FR1IByte);
//Transfers the Function Register 1 Data Bytes//
SPItransfer24(FR1DBytes);
//Transfers the Channel Select Register Information Byte//
SPItransfer8(CSRIByte);
//Transfers the Channel Select Register Data Byte for CH0
SPItransfer8(CSRCH0);
//Transfers the Channel Frequency Tuning Word Information Byte//
SPItransfer8(CFTWIByte);
//Transfers the Channel 0 Frequency Tuning Word//
SPItransfer32(CFTWCH0);
//Transfers the Channel Select Register Information Byte//
SPItransfer8(CSRIByte);
//Transfers the Channel Select Register Data Byte for CH1
SPItransfer8(CSRCH1);
//Transfers the Channel Frequency Tuning Word Information Byte//
SPItransfer8(CFTWIByte);
//Transfers the Channel 1 Frequency Tuning Word//
SPItransfer32(CFTWCH1);
//Transfers the Channel Select Register Information Byte//
SPItransfer8(CSRIByte);
//Transfers the Channel Select Register Data Byte for CH2
SPItransfer8(CSRCH2);
//Transfers the Channel Frequency Tuning Word Information Byte//
SPItransfer8(CFTWIByte);
//Transfers the Channel 2 Frequency Tuning Word//
SPItransfer32(CFTWCH2);
//Toggle I/O_Update to load data into DDS//
PORTEbits.RE2 = 1;
PORTEbits.RE2 = 0;
//Loop holding RA6 low to prevent further data transmission//
while (1)
{
PORTAbits.RA6 = 0;
}
}
以下是 MCC 生成的配置文件：
// CONFIG1L
#pragma config RETEN = OFF // VREG Sleep Enable bit->Ultra low-power regulator is Disabled (Controlled by REGSLP bit)
#pragma config INTOSCSEL = HIGH // LF-INTOSC Low-power Enable bit->LF-INTOSC in High-power mode during Sleep
#pragma config SOSCSEL = DIG // SOSC Power Selection and mode Configuration bits->Digital (SCLKI) mode
#pragma config XINST = OFF // Extended Instruction Set->Disabled
// CONFIG1H
#pragma config FOSC = INTIO2 // Oscillator->Internal RC oscillator
#pragma config PLLCFG = OFF // PLL x4 Enable bit->Disabled
#pragma config FCMEN = OFF // Fail-Safe Clock Monitor->Disabled
#pragma config IESO = OFF // Internal External Oscillator Switch Over Mode->Disabled
// CONFIG2L
#pragma config PWRTEN = OFF // Power Up Timer->Disabled
#pragma config BOREN = SBORDIS // Brown Out Detect->Enabled in hardware, SBOREN disabled
#pragma config BORV = 3 // Brown-out Reset Voltage bits->1.8V
#pragma config BORPWR = ZPBORMV // BORMV Power level->ZPBORMV instead of BORMV is selected
// CONFIG2H
#pragma config WDTEN = OFF // Watchdog Timer->WDT disabled in hardware; SWDTEN bit disabled
#pragma config WDTPS = 1048576 // Watchdog Postscaler->1:1048576
// CONFIG3H
#pragma config CANMX = PORTB // ECAN Mux bit->ECAN TX and RX pins are located on RB2 and RB3, respectively
#pragma config MSSPMSK = MSK7 // MSSP address masking->7 Bit address masking mode
#pragma config MCLRE = OFF // Master Clear Enable->MCLR Disabled, RE3 Enabled
// CONFIG4L
#pragma config STVREN = ON // Stack Overflow Reset->Enabled
#pragma config BBSIZ = BB2K // Boot Block Size->2K word Boot Block size
// CONFIG5L
#pragma config CP0 = OFF // Code Protect 00800-03FFF->Disabled
#pragma config CP1 = OFF // Code Protect 04000-07FFF->Disabled
#pragma config CP2 = OFF // Code Protect 08000-0BFFF->Disabled
#pragma config CP3 = OFF // Code Protect 0C000-0FFFF->Disabled
// CONFIG5H
#pragma config CPB = OFF // Code Protect Boot->Disabled
#pragma config CPD = OFF // Data EE Read Protect->Disabled
// CONFIG6L
#pragma config WRT0 = OFF // Table Write Protect 00800-03FFF->Disabled
#pragma config WRT1 = OFF // Table Write Protect 04000-07FFF->Disabled
#pragma config WRT2 = OFF // Table Write Protect 08000-0BFFF->Disabled
#pragma config WRT3 = OFF // Table Write Protect 0C000-0FFFF->Disabled
// CONFIG6H
#pragma config WRTC = OFF // Config. Write Protect->Disabled
#pragma config WRTB = OFF // Table Write Protect Boot->Disabled
#pragma config WRTD = OFF // Data EE Write Protect->Disabled
// CONFIG7L
#pragma config EBTR0 = OFF // Table Read Protect 00800-03FFF->Disabled
#pragma config EBTR1 = OFF // Table Read Protect 04000-07FFF->Disabled
#pragma config EBTR2 = OFF // Table Read Protect 08000-0BFFF->Disabled
#pragma config EBTR3 = OFF // Table Read Protect 0C000-0FFFF->Disabled
// CONFIG7H
#pragma config EBTRB = OFF // Table Read Protect Boot->Disabled
错误实际上在 LATA5 = 0; 上面的行中。宏 __delay_ms 在 pic18.h 中定义为：
_delay((unsigned long)((x)*(_XTAL_FREQ/4000000.0)))
并且需要一个语句终止符。你少了一个分号。将行更改为：
__delay_ms(10);
我是 PIC18 编程的新手 micro-controllers，当我尝试编译我的代码时，我总是收到编译错误 195。我使用的 PIC 是 PIC18F46k80，我尝试为其编程的应用程序是针对已经嵌入 PIC 的硬件，所以我无法更改 Pin 配置（我没有设计硬件).我试图让我的 PIC 通过 bit-banging 执行稍微修改的 SPI 协议，因为内部外围设备的正确引脚尚未连接。每当我尝试设置 RA6 或 RA5 时，我都会将 运行 保留在这个编译错误中，即使（我认为）我已经配置了引脚以使其可写（不提供内部时钟）。具体来说，我在尝试设置 LATA6 = x 或 LATA5 = x 时遇到错误。在 MPLAB X 中，我编写 LATA6 或 LATA5 的每一期都被突出显示。有人可以帮我 writing/setting 这些图钉吗？ 以下代码的任何实例都会导致问题：
LATA5 = 0;
//or
LAT6 = 0;
//or
LAT6 = 1;
如果需要，我可以发送整个文件，包括 headers 和配置文件 :) 欢迎任何帮助。
完整代码如下：
#include "mcc_generated_files/mcc.h"
#include <stdio.h>
#include<stdlib.h>
#include<xc.h>
//Define words for transfer//
uint8_t FR1IByte = 0x01;
int FR1DBytes = 0x900000;
uint8_t CSRIByte = 0x00;
uint8_t CSRCH0 = 0x10;
uint8_t CSRCH1 = 0x20;
uint8_t CSRCH2 = 0x40;
uint8_t CFTWIByte = 0x04;
uint32_t CFTWCH0 = 0x42680000;
uint32_t CFTWCH1 = 0x1F400000;
uint32_t CFTWCH2 = 0x3E800000;
//Functions to perform SPI//
void SPItransfer8( uint8_t byte)
{
// local variable declaration
int i;
for (i = 0; i <8; i++){ //compares MSB with mask. If it matches, it will transfer a 1//
if(byte & 0x80)
{
LATC5 = 1;
}
else
{
LATC5 = 0;
}
// Pulses clock for transfer of data//
LATA6 = 1;
LATA6 = 0;
// Logical shift left so that next byte can be read//
byte <<= 1;
}
}
void SPItransfer24( int bytes)
{
// local variable declaration
int i;
for (i = 0; i <24; i++);
{ //compares MSB with mask. If it matches, it will transfer a 1//
if(bytes & 0x800000)
{
LATC5 = 1;
}
else
{
LATC5 = 0;
}
// Pulses clock for transfer of data//
LATA6 = 1;
LATA6 = 0;
// Logical shift left so that next byte can be read//
bytes <<= 1;
}
}
void SPItransfer32( uint32_t bytes)
{
// local variable declaration
int i;
for (i = 0; i <32; i++);
{ //compares MSB with mask. If it matches, it will transfer a 1//
if(bytes & 0x80000000)
{
LATC5 = 1;
}
else
{
LATC5 = 0;
}
// Pulses clock for transfer of data//
LATA6 = 1;
LATA6 = 0;
// Logical shift left so that next byte can be read//
bytes <<= 1;
}
}
void main(void)
{
TRISE = 0x03;
TRISA = 0b1001111;
// Initialize the device//
SYSTEM_Initialize();
// Perform master reset on DDS to set the device to its default state (Active high on E2)//
LATE1 = 1;
LATE1 = 0;
// Delay to allow the system to load (PLL takes time to lock) //
__delay_ms(10)
//Set RA5 to low to prevent power down//
LATA5 = 0;
//Set RA6 to low for SPI clock//
LATA6 = 0;
//Transfers the Function Register 1 Information Byte//
SPItransfer8(FR1IByte);
//Transfers the Function Register 1 Data Bytes//
SPItransfer24(FR1DBytes);
//Transfers the Channel Select Register Information Byte//
SPItransfer8(CSRIByte);
//Transfers the Channel Select Register Data Byte for CH0
SPItransfer8(CSRCH0);
//Transfers the Channel Frequency Tuning Word Information Byte//
SPItransfer8(CFTWIByte);
//Transfers the Channel 0 Frequency Tuning Word//
SPItransfer32(CFTWCH0);
//Transfers the Channel Select Register Information Byte//
SPItransfer8(CSRIByte);
//Transfers the Channel Select Register Data Byte for CH1
SPItransfer8(CSRCH1);
//Transfers the Channel Frequency Tuning Word Information Byte//
SPItransfer8(CFTWIByte);
//Transfers the Channel 1 Frequency Tuning Word//
SPItransfer32(CFTWCH1);
//Transfers the Channel Select Register Information Byte//
SPItransfer8(CSRIByte);
//Transfers the Channel Select Register Data Byte for CH2
SPItransfer8(CSRCH2);
//Transfers the Channel Frequency Tuning Word Information Byte//
SPItransfer8(CFTWIByte);
//Transfers the Channel 2 Frequency Tuning Word//
SPItransfer32(CFTWCH2);
//Toggle I/O_Update to load data into DDS//
PORTEbits.RE2 = 1;
PORTEbits.RE2 = 0;
//Loop holding RA6 low to prevent further data transmission//
while (1)
{
PORTAbits.RA6 = 0;
}
}
以下是 MCC 生成的配置文件：
// CONFIG1L
#pragma config RETEN = OFF // VREG Sleep Enable bit->Ultra low-power regulator is Disabled (Controlled by REGSLP bit)
#pragma config INTOSCSEL = HIGH // LF-INTOSC Low-power Enable bit->LF-INTOSC in High-power mode during Sleep
#pragma config SOSCSEL = DIG // SOSC Power Selection and mode Configuration bits->Digital (SCLKI) mode
#pragma config XINST = OFF // Extended Instruction Set->Disabled
// CONFIG1H
#pragma config FOSC = INTIO2 // Oscillator->Internal RC oscillator
#pragma config PLLCFG = OFF // PLL x4 Enable bit->Disabled
#pragma config FCMEN = OFF // Fail-Safe Clock Monitor->Disabled
#pragma config IESO = OFF // Internal External Oscillator Switch Over Mode->Disabled
// CONFIG2L
#pragma config PWRTEN = OFF // Power Up Timer->Disabled
#pragma config BOREN = SBORDIS // Brown Out Detect->Enabled in hardware, SBOREN disabled
#pragma config BORV = 3 // Brown-out Reset Voltage bits->1.8V
#pragma config BORPWR = ZPBORMV // BORMV Power level->ZPBORMV instead of BORMV is selected
// CONFIG2H
#pragma config WDTEN = OFF // Watchdog Timer->WDT disabled in hardware; SWDTEN bit disabled
#pragma config WDTPS = 1048576 // Watchdog Postscaler->1:1048576
// CONFIG3H
#pragma config CANMX = PORTB // ECAN Mux bit->ECAN TX and RX pins are located on RB2 and RB3, respectively
#pragma config MSSPMSK = MSK7 // MSSP address masking->7 Bit address masking mode
#pragma config MCLRE = OFF // Master Clear Enable->MCLR Disabled, RE3 Enabled
// CONFIG4L
#pragma config STVREN = ON // Stack Overflow Reset->Enabled
#pragma config BBSIZ = BB2K // Boot Block Size->2K word Boot Block size
// CONFIG5L
#pragma config CP0 = OFF // Code Protect 00800-03FFF->Disabled
#pragma config CP1 = OFF // Code Protect 04000-07FFF->Disabled
#pragma config CP2 = OFF // Code Protect 08000-0BFFF->Disabled
#pragma config CP3 = OFF // Code Protect 0C000-0FFFF->Disabled
// CONFIG5H
#pragma config CPB = OFF // Code Protect Boot->Disabled
#pragma config CPD = OFF // Data EE Read Protect->Disabled
// CONFIG6L
#pragma config WRT0 = OFF // Table Write Protect 00800-03FFF->Disabled
#pragma config WRT1 = OFF // Table Write Protect 04000-07FFF->Disabled
#pragma config WRT2 = OFF // Table Write Protect 08000-0BFFF->Disabled
#pragma config WRT3 = OFF // Table Write Protect 0C000-0FFFF->Disabled
// CONFIG6H
#pragma config WRTC = OFF // Config. Write Protect->Disabled
#pragma config WRTB = OFF // Table Write Protect Boot->Disabled
#pragma config WRTD = OFF // Data EE Write Protect->Disabled
// CONFIG7L
#pragma config EBTR0 = OFF // Table Read Protect 00800-03FFF->Disabled
#pragma config EBTR1 = OFF // Table Read Protect 04000-07FFF->Disabled
#pragma config EBTR2 = OFF // Table Read Protect 08000-0BFFF->Disabled
#pragma config EBTR3 = OFF // Table Read Protect 0C000-0FFFF->Disabled
// CONFIG7H
#pragma config EBTRB = OFF // Table Read Protect Boot->Disabled
错误实际上在 LATA5 = 0; 上面的行中。宏 __delay_ms 在 pic18.h 中定义为：
_delay((unsigned long)((x)*(_XTAL_FREQ/4000000.0)))
并且需要一个语句终止符。你少了一个分号。将行更改为：
__delay_ms(10);