modelsim 中的 Verilog 错误 - 靠近“=”：语法错误，意外的“=”，需要 IDENTIFIER 或 TYPE_IDENTIFIER 或 NETTYPE_IDENTIFIER

Question

我在 modelsim 10.4 中遇到以下错误：

错误：(vlog-13069) D:/divya/verilog/pipelined alu/alu.v(5)：靠近“=”：语法错误，意外的“=”，需要 IDENTIFIER 或 TYPE_IDENTIFIER 或网络TYPE_IDENTIFIER.

代码：

module func(output reg[15:0] out,input[15:0] a,b,input[3:0] select);


case(select)

0:out=a+b;

1:out=a-b;

2:out=a*b;

3:out=a;

4:out=b;

5:out=a&b;

6:out=a|b;

7:out=a^b;

8:out=~a;

9:out=~b;

10:out=a>>1;
11:out=a<<1;

default:out=16'hxxxx;

endcase

endmodule

Answer 1

当你像上面那样实现组合逻辑时，你需要确保将功能描述放在一个过程块中，比如 always @(*) 或 assign 语句（你使用哪一个取决于关于逻辑的长度和其他次要因素）。下面是您的代码，带有一些格式（请记住，编码风格不仅仅是美学；它还有助于发现错误并使阅读代码更容易！）：

module func(output reg [15:0] out,
            input [15:0] a, b,
            input [3:0] select); // I like to break up io on multiple lines to make it easier to read

  always @(*) begin // Need to put logic in a procedural block!
    case(select)
    0: out = a + b;
    1: out = a - b;
    2: out = a * b; // Note that this would take quite a bit of logic compared to all the other operations here, combinational multiply take alot of gates
    3: out = a;
    4: out = b;
    5: out = a & b;
    6: out = a | b;
    7: out = a ^ b;
    8: out = ~a;
    9: out = ~b;
    10: out = a >> 1;
    11: out = a << 1;
    default: out = 16'hxxxx;
    endcase
  end
endmodule

modelsim 中的 Verilog 错误 - 靠近“=”：语法错误，意外的“=”，需要 IDENTIFIER 或 TYPE_IDENTIFIER 或 NETTYPE_IDENTIFIER

Verilog error in modelsim- near "=": syntax error, unexpected '=', expecting IDENTIFIER or TYPE_IDENTIFIER or NETTYPE_IDENTIFIER

verilog

simulation

hdl

modelsim