Verilog RTL：将数字数据写入预定义存储器 "address"

Question

我有 [8:0] 数字数据输入。我想预先定义这些值并用唯一地址存储它们，这样我以后就可以通过调用它们的地址值在我的逻辑中访问它们。

不完全确定，我正在做类似的事情（此外，这是针对 Verilog RTL（可合成）的：

reg array[8:0];
array[8] = 9'b000000000;
array[7] = 9'b000000001;
array[6] = 9'b000000010;
array[5] = 9'b000000011;
array[4] = 9'b000000100;
array[3] = 9'b000000101;
array[2] = 9'b000000111;
array[1] = 9'b000001000;
array[0] = 9'b000000000;

我不确定，这只是我的想法。

Answer 1

如果您想创建 LUT（这基本上是您所建议的），那么您就走对了：

reg [8:0] lut [8:0]; // Its an array of 9 elements (0 through 8 after the variable name), each of which is 9 bits wide (before the variable name)
assign lut[8] = 9'b000000000; // If there is a pattern to the array, use generate statement and loops to initialize it, Im just doing it one-by-one here
assign lut[7] = 9'b000000001;
assign lut[6] = 9'b000000010;
assign lut[5] = 9'b000000011;
assign lut[4] = 9'b000000100;
assign lut[3] = 9'b000000101;
assign lut[2] = 9'b000000111;
assign lut[1] = 9'b000001000;
assign lut[0] = 9'b000000000;

Verilog RTL：将数字数据写入预定义存储器 "address"

Verilog RTL: Writing Digital data into predefined memory "address"

verilog

register-transfer-level