使用 VHDL 的 RTL 硬件设计，示例 7.1

Question

7.1 - 考虑一个可以执行四种运算的算术电路：a+b、a-b、a+1 和 a-1，其中 a 和 b 是 16 位无符号数，所需运算由 a 2 指定-位控制信号，ctrl.

是否可以只用一个加法器而不使用时序逻辑来设计这个电路

我用 2 的互补逻辑设计了这个电路，但我不能添加逻辑 (a + (not b) + 1) 只有一个没有存储器组件的加法器

    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.NUMERIC_STD.ALL;

    entity Ex_7_1_b is
         generic( BUS_WIDTH : integer := 16 );
        port ( a : in  STD_LOGIC_VECTOR (BUS_WIDTH - 1 downto 0);
               b : in  STD_LOGIC_VECTOR (BUS_WIDTH - 1 downto 0);
               ctrl : in  STD_LOGIC_VECTOR (1 downto 0);
               y : out  STD_LOGIC_VECTOR (BUS_WIDTH - 1 downto 0)
                );
    end Ex_7_1_b;

    architecture Behavioral of Ex_7_1_b is
        signal adder : unsigned(BUS_WIDTH - 1 downto 0);
        signal mux_sign : unsigned(BUS_WIDTH - 1 downto 0);
        signal mux_inp_sel : unsigned(BUS_WIDTH - 1 downto 0);
        signal mux_val : unsigned(BUS_WIDTH - 1 downto 0);
        signal result : unsigned(BUS_WIDTH - 1 downto 0);
    begin
        mux_val <= to_unsigned(0, mux_val'length) when ctrl(1) = '1' else to_unsigned(1, mux_val'length);
        mux_inp_sel <= mux_val when ctrl(0) = '1' else unsigned(b);
        mux_sign <= not (mux_inp_sel) when ctrl(1) = '1' else mux_inp_sel;

        result <= unsigned(a) + mux_sign;
        y <= std_logic_vector(result);

    end Behavioral;

Answer 1

我设计了这个电路 Renaud Pacalet 贡献了。

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity Ex_7_1_b is
    generic( g_BUS_WIDTH : integer := 16    );
    port ( 
            i_a : in  std_logic_vector (g_BUS_WIDTH - 1 downto 0);
            i_b : in  std_logic_vector (g_BUS_WIDTH - 1 downto 0);
            i_ctrl : in  std_logic_vector (1 downto 0);
            o_y : out  std_logic_vector (g_BUS_WIDTH - 1 downto 0)
         );
end Ex_7_1_b;

architecture RTL of Ex_7_1_b is
    signal r_A_Ext, r_B_Ext : unsigned(g_BUS_WIDTH downto 0);
    signal r_Carry_In : std_logic;
    signal r_Adder : unsigned(g_BUS_WIDTH - 1 downto 0);
    signal w_Mux_Inv : unsigned(g_BUS_WIDTH - 1 downto 0);
    signal w_Mux_Sel : unsigned(g_BUS_WIDTH - 1 downto 0);
    signal r_Result : unsigned(g_BUS_WIDTH downto 0);
begin
    r_A_Ext <= unsigned(i_a & '1');

    w_Mux_Sel <= to_unsigned(1, w_Mux_Sel'length) when i_ctrl(1) = '1' else unsigned(i_b);
    w_Mux_Inv <= not (w_Mux_Sel) when i_ctrl(0) = '1' else w_Mux_Sel;

    r_Carry_In <= '1' when i_ctrl(0) = '1' else '0';

    r_B_Ext <= w_Mux_Inv & r_Carry_In;

    r_Result <= r_A_Ext + r_B_Ext;
    o_y <= std_logic_vector(r_Result(g_BUS_WIDTH downto 1));
end RTL;

Answer 2

您自己找到的解决方案很好，但它使用 17 位加法器而不是 16 位加法器。使用足够智能的合成器，它应该不会有任何区别。为了完整起见，这里还有另一个 16 位（并且稍微简单一些）的解决方案：

architecture RTL of Ex_7_1_b is
    signal x, y0, y1: unsigned(g_BUS_WIDTH - 1 downto 0);
begin
    x   <= unsigned(i_a);
    y0  <= unsigned(i_b) when i_ctrl(1) = '0' else x"0001";
    y1  <= not y0 when i_ctrl(0) = '1' else y0;
    o_y <= std_logic_vector(x + y1 + i_ctrl(0));
end architecture RTL;

注意：这仅适用于定义了 unsigned 和 std_logic 添加的 VHDL 2008。如果您必须使用旧版本的 VHDL 标准，请改用以下版本：

architecture RTL of Ex_7_1_b is
    signal x, y0, y1: unsigned(g_BUS_WIDTH - 1 downto 0);
    signal c: natural range 0 to 1;
begin
    x   <= unsigned(i_a);
    y0  <= unsigned(i_b) when i_ctrl(1) = '0' else x"0001";
    y1  <= not y0 when i_ctrl(0) = '1' else y0;
    c   <= 1 when i_ctrl(0) = '1' else 0;
    o_y <= std_logic_vector(x + y1 + c);
end architecture RTL;

使用 VHDL 的 RTL 硬件设计，示例 7.1

RTL Hardware Design Using VHDL, Example 7.1

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