Verilog 中的 FSM 状态机

Question

如果input没有reset，如何设置初始状态为state_0？

reg[2:0]    state;


localparam  s0 = 3'b000, s1 = 3'b001, s2 = 3'b010, s3 = 3'b011, s4 = 
3'b100, s5 = 3'b101;    
assign  state = s0; /* NOT SURE IF THIS IS RIGHT!*/


localparam  i=0, j=64, k=0, h=0; 


always @ ( posedge clk ) begin

case( state )

        s0: ........

Answer 1

不，那是行不通的，因为 assign 语句会一直强制 state = s0。编译器还会抱怨多个驱动程序设置 state。如果没有复位信号，一种选择是：

initial begin
  // set any initial values
  state = s0;
end

这将代替 assign 语句。这在模拟中效果很好，但更好的做法是修改您的状态逻辑：

localparam  s0 = 3'b000, s1 = 3'b001, s2 = 3'b010, s3 = 3'b011, s4 = 3'b100, s5 = 3'b101;
reg [2:0] state, next_state;

always @(posedge clk) begin
  state <= next_state;
end

always @(state) begin
  case (state)
  // modify this state logic to reflect your FSM
  s0: next_state <= s1;
  s1: next_state <= s2;
  s2: next_state <= s3;
  s3: next_state <= s4;
  s4: next_state <= s5;
  s5: next_state <= s0;
  // this controls the behavior at bringup w/o a reset
  // you should include a default case even with a reset
  default: next_state <= s0;
  endcase
end

always @(state) begin
  case (state)
  // modify this output logic to reflect your FSM
  s0: // set your output signals accordingly
  s1: // set your output signals accordingly
  s2: // set your output signals accordingly
  s3: // set your output signals accordingly
  s4: // set your output signals accordingly
  s5: // set your output signals accordingly
  // this controls the behavior at bringup w/o a reset
  // you should include a default case even with a reset
  default: // set all outputs to 0
  endcase
end

将逻辑分离到时钟 always 块和上面的组合状态转换逻辑有助于创建无锁存器设计。我知道这比你问的要多，但这种编码风格有助于创建良好的综合设计。

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